Multi-core hardware semaphore in non-architectural address space
First Claim
Patent Images
1. A microprocessor, comprising:
- a plurality of processing cores;
a plurality of resources, shared by the plurality of processing cores; and
a plurality of hardware semaphores, each associated with a different one of the plurality of resources, wherein each hardware semaphore is readable and writeable by the plurality of processing cores over a bus at a predetermined address within a non-architectural address space of the cores, wherein the non-architectural space can only be accessed by microcode running on the processing cores;
microcode on each of the plurality of cores that associates each one of the plurality hardware semaphores with ownership of a different shared resource and which is configured to read and write the hardware semaphores;
wherein each of the plurality of processing cores is configured to write to a selected hardware semaphore to request ownership of an associated shared resource and to read from the selected hardware semaphore to determine whether or not the ownership was obtained; and
wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to relinquish ownership of the associated shared resource.
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Abstract
A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.
113 Citations
22 Claims
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1. A microprocessor, comprising:
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a plurality of processing cores; a plurality of resources, shared by the plurality of processing cores; and a plurality of hardware semaphores, each associated with a different one of the plurality of resources, wherein each hardware semaphore is readable and writeable by the plurality of processing cores over a bus at a predetermined address within a non-architectural address space of the cores, wherein the non-architectural space can only be accessed by microcode running on the processing cores; microcode on each of the plurality of cores that associates each one of the plurality hardware semaphores with ownership of a different shared resource and which is configured to read and write the hardware semaphores; wherein each of the plurality of processing cores is configured to write to a selected hardware semaphore to request ownership of an associated shared resource and to read from the selected hardware semaphore to determine whether or not the ownership was obtained; and wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to relinquish ownership of the associated shared resource. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for operating a microprocessor having a plurality of processing cores and a resource shared by the plurality of processing cores, the method comprising:
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by each of the plurality of processing cores, using microcode to write to a hardware semaphore at a predetermined address within a non-architectural address space to request ownership of the shared resource, wherein the hardware semaphore is readable and writeable by each of the plurality of processing cores through a bus that provides the non-architectural address space for the hardware semaphore; by each of the plurality of processing cores, reading from the hardware semaphore to determine whether or not the ownership was obtained; by each of the plurality of processing cores, accessing the shared resource only if ownership was obtained; and by each of the plurality of processing cores, writing to the hardware semaphore to relinquish ownership of the shared resource after ownership was obtained; wherein the non-architectural space can only be accessed by microcode running on the processing cores. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
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computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising; first program code for specifying a plurality of processing cores; second program code for specifying a plurality of resources, shared by the plurality of processing cores; and third program code for specifying a plurality of hardware semaphores, each associated with a different one of the plurality of resources, wherein each hardware semaphore is readable and writeable by the plurality of processing cores over a bus at a predetermined address within a non-architectural address space of the cores, wherein the non-architectural space can only be accessed by microcode running on the processing cores; forth program code for specifying microcode for each of the plurality of cores that associates each one of the plurality hardware semaphores with ownership of a different shared resource and which is configured to read and write the hardware semaphores; and wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to request ownership of an associated shared resource and to read from the selected hardware semaphore to determine whether or not the ownership was obtained; and wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to relinquish ownership of the shared resource. - View Dependent Claims (22)
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Specification