Multi-core hardware semaphore in non-architectural address space

• US 9,898,303 B2
• Filed: 05/19/2014
• Issued: 02/20/2018
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Assistant Examiner(s): Wang, Edward
• Application Number:
  US14/281,585
• Publication Number:
  US 20150067250A1
• Time in Patent Office: 1,373 Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

Claims

1. A microprocessor, comprising:

a plurality of processing cores;

a plurality of resources, shared by the plurality of processing cores; and

a plurality of hardware semaphores, each associated with a different one of the plurality of resources, wherein each hardware semaphore is readable and writeable by the plurality of processing cores over a bus at a predetermined address within a non-architectural address space of the cores, wherein the non-architectural space can only be accessed by microcode running on the processing cores;

microcode on each of the plurality of cores that associates each one of the plurality hardware semaphores with ownership of a different shared resource and which is configured to read and write the hardware semaphores;

wherein each of the plurality of processing cores is configured to write to a selected hardware semaphore to request ownership of an associated shared resource and to read from the selected hardware semaphore to determine whether or not the ownership was obtained; and

wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to relinquish ownership of the associated shared resource.

2. The microprocessor of claim 1, wherein one of the shared resources comprises a cache memory associated shared by the plurality of processing cores.

3. The microprocessor of claim 2, wherein each of the plurality of processing cores is configured to write and read the hardware semaphore associated with the shared cache memory until it has obtained the ownership of the shared cache memory before performing a cache control operation to the shared cache memory.

4. The microprocessor of claim 3, wherein the cache control operation to the shared cache memory comprises a write back of modified cache lines in the shared cache memory to system memory and an invalidation of the shared cache memory.

5. The microprocessor of claim 1, wherein one of the associated shared resources comprises a non-architectural memory readable and writeable by each of the plurality of processing cores.

6. The microprocessor of claim 5, wherein the non-architectural memory is configured to store a state of a trusted platform module (TPM) implemented in microcode on at most one of the plurality of processing cores at any instant of time.

7. The microprocessor of claim 6, wherein each of the plurality of processing cores is configured to first obtain ownership of the TPM state stored in the non-architectural memory via the hardware semaphore before the core reads the TPM state from the non-architectural memory and begins implementing the TPM.

8. The microprocessor of claim 1, wherein one of the associated shared resources comprises a control register that controls individually an aspect of operation of each of the plurality of processing cores.

9. The microprocessor of claim 8, wherein each of the plurality of processing cores is configured to first obtain ownership of the control register via an associated hardware semaphore before the core updates the control register.

10. The microprocessor of claim 9, wherein the control register includes a separate respective field for each of the plurality of processing cores for controlling the operation aspect of the core, wherein to update the respective field for only the core but none of the other plurality of processing cores, the core reads a current value from the control register, modifies the respective field of a core portion of the current value, and writes the modified current value to the control register.

11. The microprocessor of claim 10, wherein respective fields of the control register control respective bus clock ratios for the plurality of processing cores.

12. A method for operating a microprocessor having a plurality of processing cores and a resource shared by the plurality of processing cores, the method comprising:

by each of the plurality of processing cores, using microcode to write to a hardware semaphore at a predetermined address within a non-architectural address space to request ownership of the shared resource, wherein the hardware semaphore is readable and writeable by each of the plurality of processing cores through a bus that provides the non-architectural address space for the hardware semaphore;

by each of the plurality of processing cores, reading from the hardware semaphore to determine whether or not the ownership was obtained;

by each of the plurality of processing cores, accessing the shared resource only if ownership was obtained; and

by each of the plurality of processing cores, writing to the hardware semaphore to relinquish ownership of the shared resource after ownership was obtained;

wherein the non-architectural space can only be accessed by microcode running on the processing cores.

13. The method of claim 12, wherein the shared resource comprises a shared cache memory shared by the plurality of processing cores.

14. The method of claim 13, further comprising:

writing and reading the hardware semaphore until obtaining the ownership of the shared cache memory; and

performing a cache control operation to the shared cache memory after said obtaining the ownership of the shared cache memory.

15. The method of claim 14, wherein the cache control operation to the shared cache memory comprises a write back of modified cache lines in the shared cache memory to system memory and an invalidation of the shared cache memory.

16. The method of claim 12, wherein the shared resource comprises a non-architectural memory readable and writeable by each of the plurality of processing cores.

17. The method of claim 16, wherein the non-architectural memory is configured to store a state of a trusted platform module (TPM) implemented in microcode on at most one of the plurality of processing cores at any instant of time.

18. The method of claim 17, further comprising:

obtaining ownership of the TPM state stored in the non-architectural memory via the hardware semaphore; and

reading the TPM state from the non-architectural memory and implementing the TPM after said obtaining ownership.

19. The method of claim 12, wherein the shared resource comprises a control register that controls individually an aspect of operation of each of the plurality of processing cores.

20. The method of claim 19, further comprising:

obtaining ownership of the control register via the hardware semaphore; and

updating the control register after said obtaining ownership.

21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

first program code for specifying a plurality of processing cores;

second program code for specifying a plurality of resources, shared by the plurality of processing cores; and

third program code for specifying a plurality of hardware semaphores, each associated with a different one of the plurality of resources, wherein each hardware semaphore is readable and writeable by the plurality of processing cores over a bus at a predetermined address within a non-architectural address space of the cores, wherein the non-architectural space can only be accessed by microcode running on the processing cores;

forth program code for specifying microcode for each of the plurality of cores that associates each one of the plurality hardware semaphores with ownership of a different shared resource and which is configured to read and write the hardware semaphores; and

wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to request ownership of an associated shared resource and to read from the selected hardware semaphore to determine whether or not the ownership was obtained; and

wherein each of the plurality of processing cores is configured to write to the selected hardware semaphore to relinquish ownership of the shared resource.

22. The computer program product of claim 21, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, and other magnetic, optical, or electronic storage medium.