×

Memory access processing method, memory chip, and system based on memory chip interconnection

  • US 9,898,421 B2
  • Filed: 06/26/2015
  • Issued: 02/20/2018
  • Est. Priority Date: 12/28/2012
  • Status: Active Grant
First Claim
Patent Images

1. A memory access processing method based on memory chip interconnection, comprising:

  • receiving, by a first memory chip, a memory access request that carries an indication of an urgency level;

    sending, by the first memory chip according to a preconfigured routing rule and through a chip interconnect interface disposed on the first memory chip, the memory access request to a second memory chip connected with the chip interconnect interface when the first memory chip is not a target memory chip corresponding to the memory access request;

    dividing, by the second memory chip, the memory access request into at least two secondary memory access requests;

    sending, by the second memory chip, the at least two secondary memory access requests to a third memory chip and a fourth memory chip when the target memory chip is in a busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and

    continuing to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests,wherein the second memory chip is taken as the first memory chip for implementing the process, until the target memory chip corresponding to the memory access request is determined,wherein the target memory chip comprises a cache of memory access requests, andwherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×