Memory access processing method, memory chip, and system based on memory chip interconnection
First Claim
1. A memory access processing method based on memory chip interconnection, comprising:
- receiving, by a first memory chip, a memory access request that carries an indication of an urgency level;
sending, by the first memory chip according to a preconfigured routing rule and through a chip interconnect interface disposed on the first memory chip, the memory access request to a second memory chip connected with the chip interconnect interface when the first memory chip is not a target memory chip corresponding to the memory access request;
dividing, by the second memory chip, the memory access request into at least two secondary memory access requests;
sending, by the second memory chip, the at least two secondary memory access requests to a third memory chip and a fourth memory chip when the target memory chip is in a busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and
continuing to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests,wherein the second memory chip is taken as the first memory chip for implementing the process, until the target memory chip corresponding to the memory access request is determined,wherein the target memory chip comprises a cache of memory access requests, andwherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests.
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Accused Products
Abstract
A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.
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Citations
18 Claims
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1. A memory access processing method based on memory chip interconnection, comprising:
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receiving, by a first memory chip, a memory access request that carries an indication of an urgency level; sending, by the first memory chip according to a preconfigured routing rule and through a chip interconnect interface disposed on the first memory chip, the memory access request to a second memory chip connected with the chip interconnect interface when the first memory chip is not a target memory chip corresponding to the memory access request; dividing, by the second memory chip, the memory access request into at least two secondary memory access requests; sending, by the second memory chip, the at least two secondary memory access requests to a third memory chip and a fourth memory chip when the target memory chip is in a busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and continuing to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests, wherein the second memory chip is taken as the first memory chip for implementing the process, until the target memory chip corresponding to the memory access request is determined, wherein the target memory chip comprises a cache of memory access requests, and wherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 16)
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8. A memory chip, comprising:
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a receiver configured to receive a memory access request that carries an indication of an urgency level; at least one chip interconnect interface coupled to the receiver and configured to be coupled to a second memory chip; and a transmitter coupled to the at least one chip interconnect interface and configured to; send, according to a preconfigured routing rule and through a chip interconnect interface, the memory access request to the second memory chip connected with the chip interconnect interface when the memory chip is not a target memory chip corresponding to the memory access request; divide the memory access request into at least two secondary memory access requests; send the at least two secondary memory access requests to a third memory chip and a fourth memory chip when the target memory chip is in a busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and continue to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests, wherein the target memory chip comprises a cache of memory access requests, and wherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests. - View Dependent Claims (9, 10, 11, 12, 13, 14, 17)
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15. A memory access processing system based on memory chip interconnection, comprising:
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a first memory chip; and a second memory chip coupled to the first memory chip, wherein each of the first memory chip and the second memory chip comprises; a receiver configured to receive a memory access request that carries an indication of an urgency level; at least one chip interconnect interface configured to be connected to a third memory chip and a fourth memory chip; and a transmitter coupled to the at least one chip interconnect interface and configured to send, according to a preconfigured routing rule and through a chip interconnect interface, the memory access request to the third memory chip and the fourth memory chip connected with the chip interconnect interface when the first memory chip and the second memory chip are not target memory chips corresponding to the memory access request, wherein the target memory chip comprises a cache of memory access requests, and wherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests; and a memory controller coupled to the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip, wherein the memory controller is configured to; receive a primary memory access request from a processor; send the primary memory access request to at least one of the first memory chip and the second memory chip that is not in a busy state; divide the primary memory access request into at least two secondary memory access requests; send the at least two secondary memory access requests to the third memory chip and the fourth memory chip when the target memory chip is in the busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and continue to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests. - View Dependent Claims (18)
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Specification