Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

• US 9,898,616 B2
• Filed: 05/26/2015
• Issued: 02/20/2018
• Est. Priority Date: 01/06/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Frazier, Giles R., Mealey, Bruce, Nayar, Naresh
• Primary Examiner(s): Sholeman, Abu
• Application Number:
  US14/721,052
• Publication Number:
  US 20150254473A1
• Time in Patent Office: 1,001 Days
• Field of Search: 726 29, 712219, 710260
• CPC Class Codes: G06F 2009/45587 Isolation or security of virtual machine instances
• CPC Class Codes: G06F 21/6218 to a system of files or objects, e.g. local or distributed file system or database
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/45541 Bare-metal, i.e. hypervisor runs directly on hardware
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Claims

1. A method of providing hardware thread-specific information in a multi-threaded processor supporting a number of hardware threads for executing processes within multiple logical partitions, the method comprising:

maintaining the hardware thread specific information in an internal register circuit within the multi-threaded processor;

a currently-executing one of the processes detecting access to the hardware thread-specific information;

control logic within the processor determining whether or not a privilege level of the currently-executing process indicates that the currently-executing process is a process within a given one of the multiple logical partitions; and

responsive to the control logic within the processor determining that the privilege level of the currently-executing process indicates that the currently-executing process is a process within a given one of the multiple logical partitions not having full access to the hardware thread-specific information, the control logic within the processor selectively transforming the hardware thread-specific information to generate a transformed register value that indicates exclusive use of the multi-threaded processor by hardware threads executed for processes of the given logical partition, while masking hardware-thread specific information present in the internal register circuit corresponding to one or more hardware threads of the multi-threaded processor that are assigned to execute processes of another logical partition other than the given logical partition, and responding to the access with the transformed register value.

2. The method of claim 1, wherein the determining further determines that the privilege level of the currently-executing process corresponds to a hypervisor that manages the multiple logical partitions, and wherein the method further comprises responsive to determining that the currently-execution process is a process of the hypervisor, formatting the hardware thread-specific information in a manner that shows all of the hardware thread-specific information in the internal register circuit for all of the number of hardware threads supported by the multi-threaded processor.

3. The method of claim 1, wherein the transforming is performed by a circuit comprising:

a logic block that generates the a logical register value from the hardware thread-specific information in the internal register circuit to simulate the exclusive use of the multi-threaded processor by the given partition, wherein the logical register value differs from an actual value in the internal register circuit; and

a data selector coupled to the logic block that selects an output of the logic block to provide the logical register value as the transformed register value to the currently-executing process in response to the access.

4. The method of claim 1, wherein the formatting is performed by:

generating a trap interrupt when the access to the hardware thread-specific information is detected by the detecting;

transforming, by the multi-threaded processor executing an interrupt service routine that services the trap interrupt, the hardware thread-specific information in the internal register circuit to simulate the exclusive use of the multi-threaded processor by the given partition to generate a logical register value that is different than an actual value in the internal register circuit; and

replacing a return value for the access to the hardware thread-specific information with the logical register value.

5. The method of claim 1, wherein the hardware thread-specific information is the number of hardware threads supported by the multi-threaded processor, and wherein the transformed register value contains a quantity of the number of the hardware threads that are assigned to the given partition instead of the number of hardware threads supported by the multi-threaded processor.

6. The method of claim 1, wherein the hardware thread-specific information is a value dependent on a logical hardware thread number of a particular hardware thread assigned to the given partition and specified by the access, and wherein the transforming comprises:

generating an actual hardware thread number from the logical hardware thread number;

retrieving the hardware thread-specific information for the particular hardware thread using the actual hardware thread number; and

including the retrieved hardware thread-specific information in the transformed register value.

7. A multi-threaded processor core, comprising:

one or more execution units for executing instructions of multiple hardware threads;

an instruction fetch unit for fetching the instructions of the multiple hardware threads;

an instruction dispatch unit for dispatching the instructions of the multiple hardware threads to the execution units;

a first register circuit containing hardware thread-specific information;

a logic circuit for determining whether or not a privilege level of a process accessing the first register circuit indicates that the process has full access to thread-specific information contained in the first register circuit, and responsive to determining that process does not have full access to the thread-specific information, selectively transforming the hardware thread-specific information to a logical representation of the hardware thread-specific information to reflect exclusive use of the multi-threaded processor core by hardware threads executed for processes of a given logical partition executed by the multi-threaded processor core to generate a transformed register value, while masking hardware-thread specific information present in the first register circuit corresponding to one or more hardware threads of the multi-threaded processor core that are assigned to execute processes of another logical partition other than the given logical partition, and presenting the transformed register value in response to the access.

8. The multi-threaded processor core of claim 7, wherein an output of the logic circuit is presented in response to the access when the first register circuit is accessed at a privilege level lower than a hypervisor privilege level, and wherein a value of the first register circuit is presented directly in response to the access when the first register circuit is accessed at the hypervisor privilege level.

9. The multi-threaded processor core of claim 8, further comprising a data selector for selecting the output of the logic circuit when the first register circuit is accessed from the privilege level lower than the hypervisor privilege level and selecting the first register circuit when the first register circuit is accessed from the hypervisor privilege level.

10. The multi-threaded processor core of claim 7, wherein the hardware thread-specific information is the number of hardware threads supported by the multi-threaded processor core, and wherein the logical representation of the hardware thread-specific information is a number of hardware threads assigned to the given logical partition.

11. The multi-threaded processor core of claim 7, wherein the hardware thread-specific information is a value dependent on a logical hardware thread number of a particular hardware thread assigned to the given logical partition and specified when accessing the first register circuit, and wherein the logic circuit generates an actual hardware thread number from the logical hardware thread number, retrieves the hardware thread-specific information for the particular hardware thread using the actual hardware thread number, and includes the retrieved hardware thread-specific information in the transformed register value.

12. A computer system comprising:

a memory for storing program instructions and data values; and

a multi-threaded processor coupled to the memory for executing the program instructions, wherein the multi-threaded processor comprises one or more execution units for executing instructions of multiple hardware threads, an instruction fetch unit for fetching the instructions of the multiple hardware threads, an instruction dispatch unit for dispatching the instructions of the multiple hardware threads to the execution units, a first register circuit containing hardware thread-specific information, and a logic circuit for determining whether or not a privilege level of a process accessing the first register circuit indicates that the process has full access to the thread-specific information contained in the first register circuit, and responsive to determining that process does not have full access to the thread-specific information, selectively transforming the hardware thread-specific information to a logical representation of the hardware thread-specific information to reflect exclusive use of the multi-threaded processor by hardware threads executed for processes of a given logical partition executed by the multi-threaded processor to generate a transformed register value, while masking hardware-thread specific information present in the first register circuit corresponding to one or more hardware threads of the multi-threaded processor that are assigned to execute processes of another logical partition other than the given logical partition, and responding to the access with the transformed register value.

13. The computer system of claim 12, wherein an output of the logic circuit is selected when the first register circuit is accessed at a privilege level lower than a hypervisor privilege level.

14. The computer system of claim 13, wherein the multi-threaded processor further comprises a data selector for selecting the output of the logic circuit when the first register circuit is accessed from the privilege level lower than the hypervisor privilege level and selecting the first register circuit when the first register circuit is accessed from the hypervisor privilege level.

15. The computer system of claim 12, wherein the hardware thread-specific information is the number of hardware threads supported by the multi-threaded processor, and wherein the logical representation of the hardware thread-specific information is a number of hardware threads assigned to the given logical partition.

16. The computer system of claim 12, wherein the hardware thread-specific information is a value dependent on a logical hardware thread number of a particular hardware thread assigned to the given logical partition and specified when accessing the first register circuit, and wherein the logic circuit generates an actual hardware thread number from the logical hardware thread number, retrieves the hardware thread-specific information for the particular hardware thread using the actual hardware thread number, and includes the retrieved hardware thread-specific information in the transformed register value.

17. A computer program product comprising a computer-readable storage medium that is not signal or propagating wave storing program instructions for execution by a computer system, wherein the program instructions are program instructions of a hypervisor for managing multiple logical partitions executing within a processor core, wherein the program instructions comprise:

program instructions of an interrupt handler to, responsive to a trap interrupt generated upon access to an internal register circuit of a processor integrated circuit that contains hardware-thread specific information, transform the hardware thread-specific information in the internal register circuit to reflect an exclusive use of the processor core by a given logical partition by generating a logical register value that is different than an actual value in the internal register circuit; and

program instructions of the interrupt handler to replace a return value for the access to the internal register circuit containing hardware thread-specific information with the logical register value, wherein the hardware thread-specific information is a value dependent on a logical hardware thread number of a particular hardware thread assigned to the given logical partition and specified by the access to the internal register circuit, and wherein the program instructions of the interrupt handler that transform the hardware thread-specific information in the internal register circuit comprise program

instructions for generating an actual hardware thread number from the logical hardware thread number, and retrieving the hardware thread-specific information for the particular hardware thread using the actual hardware thread number, and wherein the program instructions that replace the return value replace the return value with the retrieved hardware thread-specific information.

18. The computer program product of claim 17, wherein the hardware thread-specific information is the number of hardware threads supported by the processor core, and wherein the program instructions of the interrupt handler that transform the hardware thread-specific information in the internal register circuit return a quantity of the number of the hardware threads that are assigned to the given logical partition as the logical register value.

19. A computer system comprising:

a memory for storing program instructions and data values; and

a processor coupled to the memory for executing the program instructions, wherein the program instructions are program instructions of a hypervisor for managing multiple logical partitions executing within the processor, wherein the program instructions comprise program instructions of an interrupt handler to, respo trap interrupt generated upon access to a internal register circuit of the processor that contains hardware-thread specific information by a process not having full access to the hardware-thread specific information, selectively transform the hardware thread-specific information in the internal register circuit to reflect an exclusive use of the processor core by a given logical partition by generating a logical register value that is different than an actual value in the internal register circuit, and program instructions of the interrupt handler to replace a return value for the access to the internal register circuit containing the hardware thread-specific information with the logical register value, wherein the hardware thread-specific information is a value dependent on a logical hardware thread number of a particular hardware thread assigned to the given logical partition and specified by the access to the internal register circuit, and wherein the program instructions of the interrupt handler that transform the hardware thread-specific information in the internal register circuit comprise program instructions for generating an actual hardware thread number from the logical hardware thread number, and retrieving the hardware thread-specific information for the particular hardware thread using the actual hardware thread number, and wherein the program instructions that replace the return value replace the return value with the retrieved hardware thread-specific information.

20. The computer system of claim 19, wherein the hardware thread-specific information is the number of hardware threads supported by the multi-threaded processor, and wherein the program instructions that transform return a quantity of the number of the hardware threads that are assigned to the given logical partition as the logical register value.