Fine granularity refresh

• US 9,899,074 B2
• Filed: 01/17/2017
• Issued: 02/20/2018
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Balakrishnan, Kedarnath
• Primary Examiner(s): NGUYEN, HIEN N
• Application Number:
  US15/408,126
• Publication Number:
  US 20170345482A1
• Time in Patent Office: 399 Days
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2207/2272 Latency related aspects

Abstract

A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Claims

1. A memory controller having an input for receiving memory access requests, and an output for providing memory accesses to a memory system, the memory controller comprising:

a command queue for receiving the memory access requests and having a plurality of entries and an output for providing selected memory accesses;

an arbiter coupled to said command queue for selecting entries from said command queue for dispatch to the memory system; and

a refresh logic circuit coupled to said arbiter, wherein in an on-the-fly refresh mode, said refresh logic circuit generates auto-refresh commands to the memory system with a granularity that it automatically selects in response to conditions associated with a memory bank to be refreshed and issues a number of auto-refresh commands during a refresh interval that is inversely proportional to said granularity.

2. The memory controller of claim 1, wherein when in a first state, said refresh logic circuit provides a first auto-refresh command (REF1) during said refresh interval that causes a memory to auto-refresh all of said memory bank, and when in a second state, said refresh logic circuit provides multiple auto-refresh commands during said refresh interval to auto-refresh a portion of said memory bank corresponding to said multiple auto-refresh commands.

3. The memory controller of claim 2, wherein when in a second state, said refresh logic circuit provides two second auto-refresh commands (REF2) during said refresh interval each of which causes said memory to auto-refresh one-half of said memory bank.

4. The memory controller of claim 3, wherein when in a third state, said refresh logic circuit provides four third auto-refresh commands (REF4) during said refresh interval each of which causes said memory to auto-refresh one-fourth of said memory bank.

5. The memory controller of claim 2, wherein said refresh logic circuit transitions between said first state and said second state in response to one or more of:

a number of pending refreshes to said bank, a number of pending requests to said bank, a priority of pending requests to said memory bank, and a type of pending requests to said bank.

6. The memory controller of claim 2, wherein said refresh logic circuit transitions between said first state and said second state in response to a number of pending memory access requests to said memory bank being above a predetermined threshold.

7. The memory controller of claim 2, wherein said refresh logic circuit transitions between said second state and said first state only after issuing a number of auto-refresh commands corresponding to a portion of said memory bank that is being refreshed at one time.

8. The memory controller of claim 7, wherein said refresh logic circuit transitions between said second state and said first state further when said command queue stores no memory access request to said memory bank.

9. The memory controller of claim 1, wherein in said on-the-fly refresh mode, said refresh logic circuit generates auto-refresh commands to the memory system with said granularity that it automatically selects for all banks in a given rank of the memory system.

10. The memory controller of claim 1, wherein in said on-the-fly refresh mode, said refresh logic circuit generates auto-refresh commands to the memory system with said granularity that it automatically selects for corresponding banks in multiple ranks of the memory system.

11. A memory controller comprising:

an interface having an input for receiving memory access requests, and an output;

a decoder coupled to said output of said interface for decoding said memory access requests and providing corresponding memory accesses in response;

a command queue having a first input coupled to said output of said decoder, a second input, and an output, and having a plurality of entries;

an arbiter coupled to said command queue for providing auto-refresh commands to said second input of said command queue selecting entries from said command queue for dispatch to a memory system;

a second queue having an input coupled to said output of said command queue, and an output for coupling to a memory channel; and

a refresh logic circuit coupled to said arbiter, wherein in an on-the-fly refresh mode, said refresh logic circuit generates auto-refresh commands to the memory system with a granularity that it automatically selects in response to conditions associated with a memory bank to be refreshed and issues a number of auto-refresh commands during a refresh interval that is inversely proportional to said granularity, and provides said auto-refresh commands to said arbiter.

12. The memory controller of claim 11, wherein when in a first state, said refresh logic circuit provides a first auto-refresh command (REF1) during said refresh interval that causes a memory to auto-refresh all of said memory bank, and when in a second state, said refresh logic circuit provides multiple auto-refresh commands during said refresh interval to auto-refresh a portion of said memory bank corresponding to said multiple auto-refresh commands.

13. The memory controller of claim 12, wherein when in a second state, said refresh logic circuit provides two second auto-refresh commands (REF2) during said refresh interval each of which causes said memory to auto-refresh one-half of said memory bank.

14. The memory controller of claim 13, wherein when in a third state, said refresh logic circuit provides four third auto-refresh commands (REF4) during said refresh interval each of which causes said memory to auto-refresh one-fourth of said memory bank.

15. The memory controller of claim 12, wherein said refresh logic circuit transitions between said first state and said second state in response to one or more of:

a number of pending refreshes to said bank, a number of pending requests to said bank, a priority of pending requests to said memory bank, and a type of pending requests to said bank.

16. The memory controller of claim 12, wherein said refresh logic circuit transitions between said first state and said second state in response to a number of pending memory access requests to said memory bank being above a predetermined threshold.

17. The memory controller of claim 12, wherein said refresh logic circuit transitions between said second state and said first state only after issuing a number of auto-refresh commands corresponding to a portion of said memory bank that is being refreshed at one time.

18. The memory controller of claim 17, wherein said refresh logic circuit transitions between said second state and said first state further when said command queue stores no memory access request to said memory bank.

19. The memory controller of claim 11, wherein in said on-the-fly refresh mode, said refresh logic circuit generates auto-refresh commands to the memory system with said granularity that it automatically selects for all banks in a given rank of the memory system.

20. The memory controller of claim 11, wherein in said on-the-fly refresh mode, said refresh logic circuit generates auto-refresh commands to the memory system with said granularity that it automatically selects for corresponding banks in multiple ranks of the memory system.

21. A method controlling accesses to a memory, comprising:

receiving memory access requests;

decoding the memory access requests to provide decoded memory access requests;

storing the decoded memory access requests in a command queue;

storing auto-refresh commands in said command queue;

arbitrating among said decoded memory access requests and said auto-refresh commands in said command queue to provide selected ones of said decoded memory access requests and said auto-refresh commands to the memory; and

generating said auto-refresh commands in an on-the-fly refresh mode with a granularity that is automatically selected in response to conditions associated with a memory bank to be refreshed.

22. The method of claim 21, wherein said generating comprises:

generating a number of auto-refresh commands during a refresh interval that is inversely proportional to said granularity.

23. The method of claim 22, wherein said generating comprises:

when in a first state, providing a first auto-refresh command (REF1) during said refresh interval that causes a memory to auto-refresh all of said memory bank; and

when in a second state, providing two second auto-refresh commands (REF2) during said refresh interval each of which causes said memory to auto-refresh one-half of said memory bank.

24. The method of claim 23, wherein said generating further comprises:

when in a third state, providing four refresh four (REF4) commands during said refresh interval each of which causes said memory to auto-refresh one-fourth of said memory bank.

25. The method of claim 23, further comprising:

transitioning between said first state and said second state in response to a number of pending refreshes to said memory bank in said command queue.

26. The method of claim 25, wherein said transitioning comprises:

transitioning between said first state and said second state in response to said number of pending refreshes to said bank in said command queue being above a predetermined threshold.

27. The method of claim 23, further comprises:

transitioning between said first state and said second state when said command queue stores no access request to said memory bank.

28. The method of claim 23, further comprising:

transitioning between said second state and said first state only after issuing a number of auto-refresh commands corresponding to a portion of said memory bank that is being refreshed at one time in said second state.