Write abort detection for multi-state memories

• US 9,899,077 B2
• Filed: 05/08/2017
• Issued: 02/20/2018
• Est. Priority Date: 09/21/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Hsu, Cynthia Hua-Ling, Lee, Aaron, Manohar, Abhijeet, Dutta, Deepanshu
• Primary Examiner(s): HOANG, TRI M
• Application Number:
  US15/588,968
• Publication Number:
  US 20170243638A1
• Time in Patent Office: 288 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state'"'"'s read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Claims

1. A method, comprising:

performing a search operation in a block of a nonvolatile memory for finding a last written word line, the nonvolatile memory comprising a plurality of memory cells and a plurality of word lines connected between a first end of the block and a second end of the block, each of the plurality of memory cells connected to one of the plurality of word lines, wherein the search operation comprises;

applying a first bias voltage to a first portion of the plurality of word lines;

applying a second bias voltage to a selected one of the plurality of word lines;

applying a third bias voltage to a second portion of the plurality of word lines; and

varying the first portion of the plurality of word lines, the second portion of the plurality of word lines, and the selected one of the plurality of word lines based upon a predetermined threshold until the last written word line is identified;

wherein the selected one of the plurality of word lines is located between the first portion of the plurality of word lines and the second portion of the plurality of word lines; and

wherein the third bias voltage is less than the first bias voltage.

2. The method of claim 1, further comprising setting the first bias voltage to a voltage level at which all of the plurality of memory cells connected to the first portion of the plurality of word lines are conducting.

3. The method of claim 2, wherein the voltage level is higher than a highest threshold voltage at which the plurality of memory cells connected to the first portion of the plurality of word lines conduct.

4. The method of claim 1, further comprising setting the second bias voltage to correspond to a sensing voltage of a memory cell of the plurality of memory cells that is connected to the selected one of the plurality of word lines.

5. The method of claim 1, further comprising setting the third bias voltage to correspond to a voltage level that causes an erased memory cell of the plurality of memory cells to conduct.

6. The method of claim 1, further comprising:

determining a number of the plurality of memory cells that are in the second portion of the plurality of word lines and that are conducting;

comparing the number with the predetermined threshold; and

varying the first portion of the plurality of word lines, the second portion of the plurality of word lines, and the selected one of the plurality of word lines by a first increment if the number is equal to or greater than the predetermined threshold and by a second increment if the number is less than the predetermined threshold.

7. The method of claim 6, wherein varying the first portion of the plurality of word lines, the second portion of the plurality of word lines, and the selected one of the plurality of word lines with the first increment comprises applying the second bias voltage to another selected word line of the plurality of word lines that is separated from the selected one of the plurality of word lines by the first increment;

wherein the first portion of the plurality of word lines changes to a group of the plurality of word lines extending from the another selected word line to the first end; and

wherein the second portion of the plurality of word lines changes to another group of the plurality of word lines extending from the another selected word line to the second end.

8. The method of claim 7, wherein the first increment is either eight or four.

9. The method of claim 6, wherein varying the first portion of the plurality of word lines, the second portion of the plurality of word lines, and the selected one of the plurality of word lines with the second increment comprises applying the second bias voltage to another selected word line of the plurality of word lines that is separated from the selected one of the plurality of word lines by the second increment;

wherein the first portion of the plurality of word lines changes to a group of the plurality of word lines extending from the another selected word line to the first end; and

wherein the second portion of the plurality of word lines changes to another group of the plurality of word lines extending from the another selected word line to the second end.

10. The method of claim 9, wherein the second increment is either four or one.

11. The method of claim 1, wherein the first end is a source end and the second end is a drain end, and wherein the plurality of memory cells are programmed sequentially from the source end to the drain end such that the second portion of the plurality of word lines comprises the plurality of word lines extending between the selected one of the plurality of word lines and the drain end and the first portion of the plurality of word lines comprises the plurality of word lines extending between the selected one of the plurality of word lines and the source end, and wherein the plurality of memory cells connected to the second portion of the plurality of word lines are designated to be programmed after the plurality of memory cells connected to the first portion of the plurality of word lines.

12. The method of claim 1, wherein the first end is a source end and the second end is a drain end, and wherein the plurality of memory cells are programmed sequentially from the drain end to the source end such that the second portion of the plurality of word lines comprises the plurality of word lines extending between the selected one of the plurality of word lines and the source end and the first portion of the plurality of word lines comprises the plurality of word lines extending between the selected one of the plurality of word lines and the drain end, wherein the plurality of memory cells connected to the second portion of the plurality of word lines are designated to be programmed after the plurality of memory cells connected to the first portion of the plurality of word lines.

13. A method, comprising:

performing a search operation on a block of a nonvolatile memory for finding a last written page of the block, the block comprising a plurality of memory cells and a plurality of word lines, each of the plurality of memory cells connected to one of the plurality of word lines, wherein the plurality of memory cells are programmed sequentially and the search operation for finding the last written page of the block comprises;

applying a first bias voltage to a first portion of the plurality of word lines;

applying a second bias voltage to a selected one of the plurality of word lines;

applying a third bias voltage to a second portion of the plurality of word lines;

comparing a number of the plurality of memory cells connected to the first portion of the word lines that are conducting with a pre-determined threshold;

changing the selected one of the plurality of word lines, the first portion of the plurality of word lines, and the second portion of the plurality of word lines by a first increment based upon the number being equal to or greater than the predetermined threshold;

changing the selected one of the plurality of word lines, the first portion of the plurality of word lines, and the second portion of the plurality of word lines by a second increment based upon the number being less than the predetermined threshold;

wherein the plurality of memory cells connected to the second portion of the plurality of word lines are designated to be programmed after the plurality of memory cells connected to the first portion of the plurality of word lines;

wherein the selected one of the plurality of word lines is located between the first portion of the plurality of word lines and the second portion of the plurality of word lines; and

wherein the third bias voltage corresponds to a voltage level that causes the plurality of memory cells in an erase condition to conduct.

14. The method of claim 13, wherein the third bias voltage is less than the first bias voltage.

15. A method comprising:

dividing a plurality of word lines of a nonvolatile memory into a plurality of zones, wherein each of the plurality of word lines is connected to a memory cell, and wherein each of the plurality of zones comprises a sequential group of the plurality of word lines;

applying a first bias voltage to a first portion of the plurality of zones;

applying a second bias voltage to a second portion of the plurality of zones, wherein the first bias voltage is less than the second bias voltage;

identifying one of the plurality of zones from the first portion of the plurality of zones and the second portion of the plurality of zones having a last written word line, wherein the last written word line is part of the plurality of word lines;

dividing the one of the plurality of zones having the last written word line into a plurality of sub-zones; and

identifying one of the plurality of sub-zones having the last written word line by applying the first bias voltage to a first portion of the plurality of sub-zones and the second bias voltage to a second portion of the plurality of sub-zones.

16. The method of claim 15, further comprising dividing the one of the plurality of sub-zones having the last written word into additional smaller sub-zones until the last written word line is identified.

17. The method of claim 15, wherein the first bias voltage is a voltage level that causes an erased one of the plurality of memory cells to conduct.

18. The method of claim 15, further comprising:

identifying if all of the plurality of memory cells lying within the first portion of the plurality of zones are conducting; and

identifying a zone from the second portion of the plurality of zones that is located next to first portion of the plurality of zones as having the last written word line.

19. The method of claim 15, further comprising:

identifying at least one memory cell from the plurality of memory cells in the first portion of the plurality of zones that is not conducting; and

identifying a zone of the first portion of the plurality of zones in which the at least one memory cell that is not conducting is located as having the last written word line.

20. The method of claim 15, wherein the plurality of zones comprises four zones.