Nonvolatile memory system with program step manager and method for program step management

• US 9,899,092 B2
• Filed: 02/11/2016
• Issued: 02/20/2018
• Est. Priority Date: 01/27/2016
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: Ip Gem Group, LLC
• Inventors: Micheloni, Rino
• Primary Examiner(s): Tran, Anthan
• Application Number:
  US15/042,125
• Publication Number:
  US 20170213597A1
• Time in Patent Office: 740 Days
• Field of Search: 36518517
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A Solid State Drive (SSD) that includes a host connector receptacle for connecting to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The nonvolatile memory controller is configured to perform program operations and read operations on memory cells of each of the NAND devices. The nonvolatile memory controller includes a program step circuit configured to initially program memory cells of each of the NAND devices using an initial program step voltage and is configured to change the program step voltage used to program the memory cells of each of the NAND devices during the lifetime of each of the NAND devices.

Claims

1. A nonvolatile memory controller configured to perform program operations and read operations on memory cells of a NAND device, the nonvolatile memory controller including a program step circuit configured to initially program memory cells of the NAND device by loading an initial program step voltage into trim registers of the NAND device and configured to change the program step voltage used to program the memory cells of the NAND device by loading a different program step voltage into the trim registers of the NAND device each time that an error rate of the NAND device reaches an error threshold.

2. The nonvolatile memory controller of claim 1 wherein the nonvolatile memory controller is configured to determine the error rate in lower pages of a block, determine the error rate in middle pages of the block and determine the error rate in upper pages of the block, and is further configured to use the determined error rate in lower pages of the block, the determined error rate in middle pages of the block and the determined error rate in upper pages of the block to determine that an error rate of the NAND device has reached an error threshold.

3. The nonvolatile memory controller of claim 1 further comprising an online test module configured to perform reads of memory cells of the NAND device during operation of the NAND device to determine the error rate of the NAND device.

4. The nonvolatile memory controller of claim 1 wherein the error rate is determined by reading one or more dedicated test block to determine a maximum number of errors in each dedicated test block, the determined maximum number of errors determined to be the error rate of the NAND device.

5. The nonvolatile memory controller of claim 1 wherein the nonvolatile memory controller is configured to store one or more table that indicates one or more index value and corresponding program step voltages, the program step circuit operable to index the table with one or more index to identify a corresponding program step voltage to be loaded into the trim registers of the NAND device as the different program step voltage.

6. The nonvolatile memory controller of claim 1 wherein the error threshold is a bit error rate (BER) threshold, the BER threshold set at 90% of the error correction code (ECC) limit for the NAND device.

7. The nonvolatile memory controller of claim 5 wherein the index comprises one or more of a page type index (lower middle, upper), a block topology index and a wordline number index and a layer number.

8. The nonvolatile memory controller of claim 2 wherein the nonvolatile memory controller is configured to store one or more table that indicates one or more index value and corresponding program step voltages, the program step circuit operable to index the one or more table with a page type index and one or more other index to identify a corresponding program step voltage to be loaded into the trim registers of the NAND device as the different program step voltage.

9. A Solid State Drive (SSD) comprising:

a host connector receptacle for connecting to a host computer;

a plurality of NAND devices;

a nonvolatile memory controller coupled to the host connector receptacle and coupled to each of the plurality of NAND devices, the nonvolatile memory controller configured to perform program operations and read operations on memory cells of each of the NAND devices and wherein the nonvolatile memory controller is configured to load a program step voltage corresponding to a characteristic of a NAND device of the plurality of NAND devices that is to be programmed into a trim register of the NAND device to be programmed, such that the program step voltage is stored in the trim registers of the NAND device to be programmed prior to performing the programming of the NAND device to be programmed; and

wherein the characteristic is an error rate and wherein the nonvolatile memory controller is configured to determine an error rate for each of the NAND devices, configured to determine whether each determined error rate has reached an error threshold, and each time that an error rate is determined to have reached an error threshold, a program step circuit of the nonvolatile memory controller configured to change the program step voltage to be used for programming the NAND device determined to have the error rate that has reached the error threshold to a different program step voltage.

10. A Solid State Drive (SSD) comprising:

a host connector receptacle for connecting to a host computer;

a plurality of NAND devices;

a nonvolatile memory controller coupled to the host connector receptacle and coupled to each of the plurality of NAND devices, the nonvolatile memory controller configured to store a table that indicates one or more index value and corresponding program step voltages, the one or more index value including an error rate and a page type, the nonvolatile memory controller operable to index the table with one or more index value corresponding to an error rate and a page type of the NAND device that is to be programmed to identify the program step voltage of the stored program step voltages and to load the identified program step voltage into a trim register of the NAND device to be programmed such that the identified program step voltage is stored in the trim registers of the NAND device to be programmed prior to performing the programming of the NAND device to be programmed.

11. A method for programming a memory cell of a NAND device comprising:

loading trim registers of a NAND device with an initial program step voltage;

performing program operations of the NAND device using the initial program step voltage;

performing reads of test cells of the NAND device during operation of the NAND device to determine an error rate of the NAND device;

loading a different program step voltage into the trim registers of the NAND device when the determined error rate of the NAND device reaches an error threshold;

performing program operations of the NAND device using the different program step voltage; and

continuing the performing reads, the loading and the performing program operations, wherein the error threshold is set at a value so as to maintain a bit error rate (BER) of the NAND device below an error correction code (ECC) limit of the NAND device.

12. The method of claim 11 further comprising:

forming a state machine between a nonvolatile memory controller and the NAND device.

13. The method of claim 11 wherein the performing reads of test cells of the NAND device during operation of the NAND device to determine the error rate of the NAND device further comprises reading one or more dedicated test block of the NAND device to determine a maximum number of errors in the dedicated test block, the determined maximum number of errors determined to be the error rate of the NAND device, and further wherein the error threshold is set at a value less than an error correction code (ECC) limit of the NAND device so as to maintain the bit error rate (BER) of the NAND below the ECC limit.

14. The method of claim 13 further comprising:

storing one or more table that indicates one or more index value and corresponding program step voltages; and

searching the table using the determined error rate of the NAND device to identify the different program step voltage to be used.