Semiconductor device and manufacturing method thereof

• US 9,899,267 B1
• Filed: 12/25/2016
• Issued: 02/20/2018
• Est. Priority Date: 11/23/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liou, En-Chiuan, Tung, Yu-Cheng
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US15/390,527
• Time in Patent Office: 422 Days
• Field of Search: 257374, 257510, 257513, 438220, 438296, 438359
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure.

Claims

1. A manufacturing method of a semiconductor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of fin structures, and each of the fin structures is elongated in a first direction;

forming a shallow trench isolation structure on the semiconductor substrate, wherein the shallow trench isolation structure is located between the fin structures;

forming a plurality of gate structures on the semiconductor substrate and the shallow trench isolation structure, wherein each of the gate structures is elongated in a second direction and disposed straddling at least one of the fin structures; and

forming a gate isolation structure cutting at least one of the gate structures into two gate electrodes, wherein a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure, and the step of forming the gate isolation structure comprises;

forming a recess penetrating the gate structure corresponding to the gate isolation structure, wherein the recess is formed on one of the fin structures, a part of the fin structure is removed by the step of forming the recess, and the recess comprises;

a first part;

a second part located under the first part, wherein the second part is lower than the top surface of the shallow trench isolation structure; and

a third part located under the second part, wherein a bottom surface of the third part is lower than a bottom surface of the shallow trench isolation structure; and

filling the recess with an insulation material.

2. The manufacturing method of claim 1, wherein a width of the first part is larger than a width of the second part.

3. The manufacturing method of claim 1, wherein a width of the third part is larger than a width of the second part.

4. The manufacturing method of claim 1, wherein the fin structure corresponding to the recess is cut into two sub fin structures by the recess.

5. The manufacturing method of claim 4, wherein the two sub fin structures are separated from each other by the gate isolation structure.

6. A manufacturing method of a semiconductor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of fin structures, and each of the fin structures is elongated in a first direction;

forming a shallow trench isolation structure on the semiconductor substrate, wherein the shallow trench isolation structure is located between the fin structures;

forming a plurality of gate structures on the semiconductor substrate and the shallow trench isolation structure, wherein each of the gate structures is elongated in a second direction and disposed straddling at least one of the fin structures; and

forming a gate isolation structure cutting at least one of the gate structures into two gate electrodes, wherein a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure, and the step of forming the gate isolation structure comprises;

forming a recess penetrating the gate structure corresponding to the gate isolation structure, wherein the recess is formed on one of the fin structures, a part of the fin structure is removed by the step of forming the recess, and the recess comprises;

a first part; and

a second part located under the first part, wherein the second part is lower than the top surface of the shallow trench isolation structure, and a bottom surface of the second part is higher than a bottom surface of the shallow trench isolation structure; and

filling the recess with an insulation material, wherein the part of the fin structure is removed by the step of forming the recess for forming a recessed part in the fin structure, the gate isolation structure is formed on the recessed part of the fin structure, and the recessed part of the fin structure is formed corresponding to the recess.

7. The manufacturing method of claim 6, wherein a width of the first part is larger than a width of the second part.

8. A semiconductor device, comprising:

a semiconductor substrate comprising a plurality of fin structures, wherein each of the fin structures is elongated in a first direction;

a shallow trench isolation structure disposed on the semiconductor substrate and disposed between the fin structures;

a plurality of gate electrodes disposed on the semiconductor substrate and the shallow trench isolation structure, wherein each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures; and

a gate isolation structure disposed between two of the gate electrodes adjacent with one another in the second direction, wherein a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure, and the gate isolation structure comprises;

a first section;

a second section disposed under the first section, wherein the second section is lower than the top surface of the shallow trench isolation structure; and

a third section disposed under the second section, wherein the third section is lower than a bottom surface of the shallow trench isolation structure.

9. The semiconductor device of claim 8, wherein at least one of the fin structures comprises:

two sub fin structures disposed adjacent to each other in the first direction, wherein the gate isolation structure is disposed between the two sub fin structures in the first direction.

10. The semiconductor device of claim 8, wherein a width of the third section is larger than a width of the second section.

11. The semiconductor device of claim 8, wherein a part of the first section is disposed on the shallow trench isolation structure.

12. The semiconductor device of claim 11, wherein a width of the first section is larger than a width of the second section.