Methods for manufacturing semiconductor devices

• US 9,899,270 B2
• Filed: 12/07/2012
• Issued: 02/20/2018
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Xu, Qiuxia, Zhu, Huilong, Xu, Gaobo, Zhou, Huajie, Liang, Qingqing, Chen, Dapeng, Zhao, Chao
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US14/233,320
• Publication Number:
  US 20150279745A1
• Time in Patent Office: 1,901 Days
• Field of Search: 438585, 438595, 438199, 438305, 438275, 438287, 438591, 438153, 438923
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

Claims

1. A method for manufacturing a semiconductor device having two opposite types of MOSFETs formed on one semiconductor substrate, comprising:

forming MOSFETs on the semiconductor substrate, said MOSFETs comprising source/drain regions located in the semiconductor substrate, a dummy gate stack located between the source/drain regions and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack;

removing the dummy gate stack of said MOSFETs to expose the surface of the semiconductor substrate to form a gate opening;

forming an interfacial oxide layer on the exposed surface of the semiconductor structure;

forming a high-K gate dielectric on the interfacial oxide layer within the gate opening;

forming a first metal gate layer on the high-K gate dielectric;

implanting non-metal doping ions in the first metal gate layer, the two opposite types of MOSFETs comprise a N-type MOSFET and a P-type MOSFET, and the step of implanting doping ions into the first metal gate layer comprising;

the P-type MOSFET is shielded, and the ion implantation is performed by implanting a first dopant which is one selected from a group consisting of P and As on the first metal gate layer of the N-type MOSFET; and

the N-type MOSFET is shielded, and the ion implantation is performed by implanting a second dopant which is one selected from a group consisting of B and BF(2) on the first metal gate layer of the P-type MOSFET;

forming a second metal gate layer on the first metal gate layer to fill the gate opening; and

annealing at a temperature within a range between 350 degrees Centigrade and 450 degrees Centigrade to diffuse and accumulate the non-metal doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

2. The method according to claim 1, wherein the high-K gate dielectric is made of one material selected from a group consisting of ZrO2, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO, HfLaON and any combination thereof.

3. The method according to claim 1, wherein the high-K gate dielectric has a thickness of about 1.5-5 nm.

4. The method according to claim 1, wherein the high-K gate dielectric is formed by means of Atomic Layer Deposition, Physical Vapor Deposition, or Metal Organic Chemical Vapor Deposition.

5. The method according to claim 4, wherein after the high-K gate dielectric is formed, the method further comprises an additional annealing to improve the quality of the high-K gate dielectric.

6. The method according to claim 1, wherein the first metal gate layer is made of one selected from a group consisting of TiN, TaN, MoN, WN, TaC, TaCN and any combination thereof.

7. The method according to claim 1, wherein the first meal gate layer has a thickness of about 2-10 nm.

8. The method according to claim 1, wherein the second metal gate layer is made of one selected from a group consisting of W, Ti, TiAl, Al, Mo, Ta, TiN, TaN, WN and any combination thereof.

9. The method according to claim 1, wherein in the step of implanting doping ions into the first metal gate layer, the energy and dose for ion implantation are controlled according to desired threshold voltage, so that the doping ions only distribute in the first metal gate layer.

10. The method according to claim 9, wherein the energy for ion implantation is about 0.2 KeV-30 KeV.

11. The method according to claim 9, wherein the dose for ion implantation is about 1E13-1E15 cm-2.

12. The method according to claim 1, wherein the first dopant is a dopant capable of reducing the effective work function.

13. The method according to claim 1, wherein the second dopant is a dopant capable of increasing the effective work function.

14. The method according to claim 1, wherein the annealing is performed in an inert gas atmosphere or weakly reducing atmosphere with an annealing time of about 20-90 minutes.