Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

• US 9,899,276 B1
• Filed: 09/30/2017
• Issued: 02/20/2018
• Est. Priority Date: 04/04/2016
• Status: Expired due to Fees

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
• Primary Examiner(s): Munoz, Andres
• Application Number:
  US15/721,890
• Time in Patent Office: 143 Days
• Field of Search: None
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11888 More than 3 levels of metal
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 : characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/45 : Ohmic electrodes

Abstract

A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of interlayer overlap shorts and/or leakages.

Claims

1. A process for making an integrated circuit (IC) that includes a multiplicity of standard cell library compatible, non-contact electrical measurement (NCEM)-enabled fill cells, such process including instantiating each of said NCEM-enabled fills cells by:

patterning at least first and second power rails, each in a conductive layer, with each power rail extending longitudinally in a first direction and configured for abutted instantiation with logic cells in the standard cell library;

patterning a plurality of gate (GATE) stripes, with each extending longitudinally, in a second direction perpendicular to the first direction, from at least the first power rail to at least the second power rail, each of the GATE stripes having a uniform transverse thickness and a uniform center-to-center spacing (CPP) between adjacent GATE stripes;

instantiating an NCEM pad, by;

patterning at least three first-direction stripes, each in a conductive layer, each extending longitudinally in the first direction, and each positioned in a transverse direction between the first and second power rails;

patterning at least three second-direction stripes, each in a conductive layer, each extending longitudinally in the second direction, each positioned longitudinally between the first and second power rails, and each positioned transversely between adjacent GATE stripes, such that the center-to-center spacing between adjacent second-direction stripes is CPP;

connecting each of the first-direction stripes to each of the second-direction stripes;

instantiating at least one interlayer overlap test area, by patterning a first feature and a second feature, not electrically connected to, the first feature, the first and second features partially overlapping to define a rectangular test area characterized by a major dimension and a minor dimension; and

,

patterning pad/ground wiring to (i) connect one of the first or second features to the NCEM pad and (ii) connect the other of the first or second features to at least one of the power rail.

2. A process, as defined in claim 1, wherein the process produces NCEM-enabled fill cells that are configured as interlayer-overlap-short-configured fill cells.

3. A process, as defined in claim 1, wherein the process produces NCEM-enabled fill cells that are configured as interlayer-overlap-leakage-configured fill cells.

4. A process, as defined in claim 1, wherein instantiating the NCEM pads includes patterning four first-direction stripes, each in a conductive layer, each extending longitudinally in the first direction, and each positioned in the transverse direction between the first and second power rails.

5. A process, as defined in claim 1, that includes single patterning the first-direction stripes.

6. A process, as defined in claim 1, that includes double patterning the first-direction stripes.

7. A process, as defined in claim 1, that includes triple patterning the first-direction stripes.

8. A process, as defined in claim 1, that includes single patterning the second-direction stripes.

9. A process, as defined in claim 1, that includes double patterning the second-direction stripes.

10. A process, as defined in claim 1, that includes triple patterning the second-direction stripes.

11. A process, as defined in claim 1, wherein instantiating the NCEM-enabled fill cells includes instantiating at least two interlayer overlap test areas, wired in parallel.

12. A process, as defined in claim 11, wherein each of the parallel-wired interlayer overlap test areas is identically configured.

13. A process, as defined in claim 1, wherein the process produces an IC in the form of a semiconductor wafer.

14. A process, as defined in claim 1, wherein the process produces an IC in the form of a semiconductor die.

15. A process, as defined in claim 1, wherein the process produces an IC in the form of a packaged semiconductor chip.

16. A process, as defined in claim 1, wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of the major dimension of their respective interlayer overlap test area(s).

17. A process, as defined in claim 1, wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of the minor dimension of their respective interlayer overlap test area(s).

18. A process, as defined in claim 1, wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of other patterning within expanded test area(s) that surround the interlayer overlap test area(s).

19. A process, as defined in claim 1, that further comprises instantiating additional, differently configured, NCEM-enabled fill cells, said differently configured fill cells selected from a list that consists of:

tip-to-tip-short-configured, NCEM-enabled fill cells;

tip-to-tip-leakage-configured, NCEM-enabled fill cells;

tip-to-side-short-configured, NCEM-enabled fill cells;

tip-to-side-leakage-configured, NCEM-enabled fill cells;

side-to-side-short-configured, NCEM-enabled fill cells;

side-to-side-leakage-configured, NCEM-enabled fill cells;

L-shape-interlayer-short-configured, NCEM-enabled fill cells;

L-shape-interlayer-leakage-configured, NCEM-enabled fill cells;

diagonal-short-configured, NCEM-enabled fill cells;

diagonal-leakage-configured, NCEM-enabled fill cells;

corner-short-configured, NCEM-enabled fill cells;

corner-leakage-configured, NCEM-enabled fill cells;

interlayer-overlap-short-configured, NCEM-enabled fill cells;

interlayer-overlap-leakage-configured, NCEM-enabled fill cells;

via-chamfer-short-configured, NCEM-enabled fill cells;

via-chamfer-leakage-configured, NCEM-enabled fill cells;

merged-via-short-configured, NCEM-enabled fill cells;

merged-via-leakage-configured, NCEM-enabled fill cells;

snake-open-configured, NCEM-enabled fill cells;

snake-resistance-configured, NCEM-enabled fill cells;

stitch-open-configured, NCEM-enabled fill cells;

stitch-resistance-configured, NCEM-enabled fill cells;

via-open-configured, NCEM-enabled fill cells;

via-resistance-configured, NCEM-enabled fill cells;

metal-island-open-configured, NCEM-enabled fill cells;

metal-island-resistance-configured, NCEM-enabled fill cells;

merged-via-open-configured, NCEM-enabled fill cells; and

,

merged-via-resistance-configured, NCEM-enabled fill cells.