Integrated circuits protected by substrates with cavities, and methods of manufacture

• US 9,899,281 B2
• Filed: 09/14/2016
• Issued: 02/20/2018
• Est. Priority Date: 03/12/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Shen, Hong, Woychik, Charles G., Sitaram, Arkalgud R.
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/265,148
• Publication Number:
  US 20170040237A1
• Time in Patent Office: 524 Days
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/315 : the encapsulation having a cavity
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Claims

1. A method for fabricating an electrically functioning apparatus, the method comprising:

(a) obtaining an assembly comprising;

a first substrate;

one or more modules attached and electrically connected to the first substrate, each module protruding from a top side of the assembly and comprising one or more semiconductor integrated circuits;

(b) forming a first layer on the top side of the assembly, the first layer comprising a top surface of a first material, the top surface overlying one or more first protrusions formed by the one or more modules and comprising a second protrusion over each first protrusion, the top surface comprising a laterally-extending area located at a level below a top of each second protrusion;

(c) obtaining a second substrate comprising one or more cavities; and

(d) after said forming the first layer on the top side of the assembly, bonding the second substrate to the top surface of the first layer, with at least part of each semiconductor integrated circuit being located in a corresponding cavity in the second substrate, a portion of the top surface of the first layer being bonded to a surface of a corresponding cavity in the second substrate, and a portion of the top surface of the first layer being bonded to the second substrate at said laterally-extending area, at least one said laterally-extending area extending outside the corresponding cavity;

wherein said bonding comprises directly bonding the first layer to the second substrate; and

wherein at a conclusion of said bonding, part of the top surface of the first layer is not bonded to the second substrate and is spaced from the second substrate.

2. The method of claim 1 wherein said bonding the second substrate comprises bonding the first layer to the second substrate in an area outside the one or more cavities.

3. The method of claim 2 wherein said bonding the second substrate comprises bonding the first layer to the second substrate around each said cavity.

4. The method of claim 1 wherein the first layer covers each module.

5. The method of claim 1 wherein, for each module, the first layer covers the module and an area adjacent to the module and laterally surrounding the module.

6. The method of claim 1 wherein the first layer covers the assembly.

7. The method of claim 6 wherein an entire top surface of the first layer is continuous.

8. The method of claim 1 wherein the first layer is inorganic.

9. The method of claim 1 wherein the first layer is silicon oxide.

10. The method of claim 1 wherein the first layer is metal.

11. The method of claim 1 wherein the second substrate comprises:

a constituent substrate of a selected material, the one or more cavities extending into the constituent substrate; and

a second layer of a material different from the selected material, the second layer extending into the one or more cavities; and

said bonding comprises directly bonding the first layer to the second layer.

12. The method of claim 1 wherein said part of the top surface of the first layer underlies a surface of at least one said cavity in the second substrate.

13. The method of claim 11 wherein at a conclusion of said bonding, part of the top surface of the first layer is not bonded to the second layer and is spaced from the second layer.

14. The method of claim 13 wherein said part of the top surface of the first layer underlies a surface of at least one said cavity in the second substrate.

15. A method for fabricating an electrically functioning apparatus, the method comprising:

(a) obtaining an assembly comprising;

a first substrate;

one or more modules attached and electrically connected to the first substrate, each module protruding from a top side of the assembly and comprising one or more semiconductor integrated circuits;

(b) forming a continuous first layer on the top side of the assembly, the first layer comprising a top surface of a first material, the top surface overlying one or more first protrusions formed by the one or more modules and comprising a second protrusion over each first protrusion;

(c) obtaining a second substrate comprising one or more cavities; and

(d) after said forming the first layer on the top side of the assembly, bonding the second substrate to the top surface of the first layer, with at least part of each semiconductor integrated circuit being located in a corresponding cavity in the second substrate, and a top of each second protrusion of the top surface of the first layer being bonded to a surface of a corresponding cavity in the second substrate, wherein the first layer extends outside of at least one cavity;

wherein the top surface comprises, for each second protrusion, a first area adjacent to the second protrusion and not bonded to the second substrate, the area being farther from the second substrate than is the second protrusion.

16. The method of claim 15 wherein the top surface further comprises, for each second protrusion, a second area separated from the second protrusion by the first area;

and

the second substrate is directly bonded to the top surface of the first layer at the top of each second protrusion and at each second area.

17. A method for fabricating an electrically functioning apparatus, the method comprising:

(a) obtaining an assembly comprising;

a first substrate;

one or more modules attached and electrically connected to the first substrate, each module protruding from a top side of the assembly and comprising one or more semiconductor integrated circuits;

(b) forming a continuous first layer on the top side of the assembly, the first layer comprising a top surface of a first material, the top surface overlying one or more first protrusions formed by the one or more modules and comprising a second protrusion over each first protrusion;

(c) obtaining a second substrate comprising one or more cavities, the second substrate comprising;

a constituent substrate of a selected material, the one or more cavities extending into the constituent substrate; and

a second layer of a material different from the selected material, the second layer comprising a bottom surface extending into the one or more cavities; and

(d) after said forming the first layer on the top side of the assembly, bonding the bottom surface of the second layer to the top surface of the first layer, with at least part of each semiconductor integrated circuit being located in a corresponding cavity in the second substrate, and at least a portion of each second protrusion of the top surface of the first layer being bonded to the bottom surface of the second layer in a corresponding cavity in the second substrate, and with at least part of the top surface of the first layer in the corresponding cavity not being bonded to the second layer and being farther from the second layer than a top of the second protrusion.