Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

• US 9,899,371 B2
• Filed: 09/08/2016
• Issued: 02/20/2018
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Fife, Keith G., Sanchez, Nevada J., Alie, Susan A.
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US15/259,243
• Publication Number:
  US 20160379973A1
• Time in Patent Office: 530 Days
• CPC Class Codes: A61B 8/00 Diagnosis using ultrasonic, sonic or infrasonic waves imaging of objects using sonar G01S15/00
• CPC Class Codes: A61B 8/4494 characterised by the arrangement of the transducer elements devices for short-range imaging using particular transducer elements arrangements under G01S15/8909; arrangements of transducers in generation of mechanical vibrations of infrasonic, sonic or ultrasonic frequency B06B1/0607
• CPC Class Codes: B06B 1/02 making use of electrical energy B06B1/18, B06B1/20 take precedence
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 2201/51 Electrostatic transducer
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0617 : comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors

Abstract

Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

Claims

1. A method, comprising:

forming an acoustic membrane of an ultrasonic transducer in a complementary metal oxide semiconductor (CMOS) wafer at least in part by stacking multiple layers of the CMOS wafer including at least one dielectric layer, a first metallization layer and a second metallization layer of the CMOS wafer;

forming at least one access hole to the first metallization layer of the CMOS wafer, the first metallization layer comprising an inner metal layer bounded by first and second conductive liner layers;

forming a cavity in the CMOS wafer by removing at least a portion of the inner metal layer of the first metallization layer through the at least one access hole using a selective etch, thereby releasing the acoustic membrane while substantially retaining the first and second conductive liner layers, wherein the first conductive liner layer is disposed between the cavity and a semiconductor substrate of the CMOS wafer, and the second conductive liner layer is disposed in the acoustic membrane between the cavity and the second metallization layer;

sealing the at least one access hole with an insulating material without filling the cavity; and

coupling the first and second conductive liner layers to integrated circuitry of the CMOS wafer.

2. The method of claim 1, wherein forming the acoustic membrane further comprises coupling the second metallization layer of the CMOS wafer to the second conductive liner layer of the first metallization layer with one or more conductive vias.

3. The method of claim 1, wherein coupling the first and second conductive liner layers to integrated circuitry of the CMOS wafer comprises coupling the first conductive liner layer to integrated circuitry in a semiconductor substrate of the CMOS wafer by one or more conductive vias.

4. The method of claim 1, wherein the inner metal layer comprises aluminum, and wherein using a selective etch comprises using a hydrofluoric acid etch.

5. The method of claim 4, wherein the first and second conductive liner layers comprise titanium nitride (TiN).

6. The method of claim 5, wherein the first conductive liner layer comprises a first electrode of the ultrasonic transducer, and the second conductive liner layer comprises a second electrode of the ultrasonic transducer.

7. A method of forming an ultrasound-on-chip device, the method comprising:

forming complementary metal oxide semiconductor (CMOS) integrated circuitry in a semiconductor substrate;

forming a layer stack over the CMOS integrated circuitry, the layer stack comprising a plurality of dielectric layers and a plurality of metallization layers;

at least partially removing a first metallization layer of the plurality of metallization layers, thereby forming a cavity of an ultrasonic transducer and an acoustic membrane of the ultrasonic transducer, wherein the cavity is disposed between first and second electrodes of the ultrasonic transducer, and wherein the acoustic membrane comprises at least one of the plurality of dielectric layers and a second metallization layer of the plurality of metallization layers, with the second electrode being disposed in the acoustic membrane between the cavity and the second metallization layer;

sealing the cavity while leaving the cavity unfilled; and

wherein the integrated circuitry is coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer.

8. The method of claim 7, wherein at least partially removing the first metallization layer further comprises:

forming at least one access hole to the first metallization layer; and

performing a selective etch to remove an inner metal layer of the first metallization layer.

9. The method of claim 8, wherein the first and second electrodes comprise liner layers of the first metallization layer.

10. The method of claim 9, wherein the inner metal layer comprises aluminum (Al), and the liner layers comprise titanium nitride (TiN).

11. The method of claim 8, further comprising sealing the at least one access hole following the selective etch.

12. The method of claim 7, further comprising forming a plurality of access holes around a perimeter defining the cavity.

13. The method of claim 12, further comprising sealing the plurality of access holes with plasma enhanced chemical vapor deposition (PECVD) silicon nitride.

14. A method of forming an ultrasound-on-chip device, the method comprising:

forming, in a complementary metal oxide semiconductor (CMOS) wafer, a cavity of an ultrasonic transducer and an acoustic membrane of the ultrasonic transducer, the CMOS wafer having integrated circuitry formed in a semiconductor substrate and a layer stack formed over the integrated circuitry, the layer stack comprising a plurality of dielectric layers and a plurality of metallization layers, wherein the forming the cavity further comprises;

at least partially removing a first metallization layer of the plurality of metallization layers through at least one access hole and sealing the at least one access hole while leaving the cavity unfilled, wherein the cavity is disposed between first and second electrodes of the ultrasonic transducer, and wherein the acoustic membrane comprises at least one of the plurality of dielectric layers and a second metallization layer of the plurality of metallization layers, with the second electrode being disposed in the acoustic membrane between the cavity and the second metallization layer; and

wherein the integrated circuitry is coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer.

15. The method of claim 14, wherein at least partially removing the first metallization layer further comprises:

Forming the at least one access hole to the first metallization layer; and

performing a selective etch to remove an inner metal layer of the first metallization layer.

16. The method of claim 15, wherein the first and second electrodes comprise liner layers of the first metallization layer.

17. The method of claim 16, wherein the inner metal layer comprises aluminum (Al), and the liner layers comprise titanium nitride (TiN).