Multi-gate device and method of fabrication thereof

• US 9,899,387 B2
• Filed: 11/16/2015
• Issued: 02/20/2018
• Est. Priority Date: 11/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Wu, Chung-Cheng, Huang, Ching-Fang, Hsieh, Wen-Hsing, Leung, Ying-Keung, Chung, Cheng-Ting
• Primary Examiner(s): Feeney, Brett
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US14/941,745
• Publication Number:
  US 20170141112A1
• Time in Patent Office: 827 Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.

Claims

1. A method comprising:

forming a first fin and a second fin in a first region and a second region, respectively, over a substrate, the first fin having a first source/drain region and a first channel region, the second fin having a second source/drain region and a second channel region, both of the first fin and the second fin are formed of a stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition;

forming dummy gate stacks over the first channel region and the second channel region;

removing the second epitaxial layers from a portion of the first fin to form first gaps in the first source/drain region;

after removing the second epitaxial layers from a portion of the first fin to form the first gaps in the first source/drain region, forming a spacer layer on sidewalls of the dummy gate stacks with a dielectric material while filling the first gaps with the dielectric material;

forming a third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the first source/drain region to form a first source/drain feature while the dielectric material fills the first gaps;

forming a fourth epitaxial layer over the second fin in the second source/drain region to form a second source/drain feature;

forming a dielectric layer over the first source/drain feature and the second source/drain feature;

after the forming the dielectric layer over the first and second source/drain features, removing the second epitaxial layers from a portion of the first fin in the first channel region to form second gaps between two adjacent first epitaxial layer;

after removing the second epitaxial layers, forming a first gate stack over the first fin in the first channel region, wherein first gate stack fills in the second gaps in the first channel region; and

forming a second gate stack over the second fin in the second channel region, wherein the second gate stack is disposed on sidewalls of the first and second epitaxial layers of the second fin in the second channel region.

2. The method of claim 1, wherein removing the second epitaxial layers from the portion of the first fin in the first channel region includes removing the dummy gate stack in the first channel region prior to removing the second epitaxial layer from the portion of the first fin in the first channel region, wherein forming the second gate stack over the second fin in the second channel region includes removing the dummy gate stack in the second channel region, wherein forming the second gate stack over the second fin in the second channel region includes removing a topmost first epitaxial layer prior to forming the second gate stack.

3. The method of claim 2, further comprising:

prior to removing the dummy gate stack, performing a planarization process to expose top surfaces of the dummy gate stacks.

4. The method of claim 2, wherein the removing the dummy gate stack in the first channel region includes forming a hard mask over the second region.

5. The method of claim 1, wherein the removing the second epitaxial layers from a portion of the first fin to form first gaps in the first source/drain region includes forming a hard mask over the second region prior to removing the second epitaxial layers from a portion of the first fin to form first gaps.

6. The method of claim 1, wherein the first region is an n-type field effect transistor (NFET) region and the second region is a p-type field effect transistor (PFET) region.

7. The method of claim 1, wherein the first composition comprises Si and the second composition comprises SiGe.

8. The method of claim 1, wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, doped silicate oxide, phosphosilicate glass, boron doped silicate glass, or mixtures thereof.

9. The method of claim 1, further comprising:

prior to forming dummy gate stacks over the first channel region and the second channel region, forming a dummy dielectric layer on top surfaces and sidewalls of the first fin and the second fin in the first and second channel regions.

10. The method of claim 1, further comprising:

prior to forming the third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the first source/drain region, performing an etch back to remove the dielectric material from the top surfaces and lateral surfaces of the stacks of epitaxial layers and from top surfaces of the dummy gate stacks.

11. The method of claim 1, wherein the forming the fourth epitaxial layer over the second fin in the second source/drain region to form a second source/drain feature includes forming the fourth epitaxial layer on sidewalls of the first and second epitaxial layers of the second fin in the second source/drain region.

12. The method of claim 1, further comprising:

before the forming of the third epitaxial layer, forming a hard mask over the second region; and

before the forming of the fourth epitaxial layer, removing the hard mask over the second region.

13. A method comprising:

forming a fin in a device region over a substrate, the fin having a source/drain region and a channel region, the fin being formed of a stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition;

forming a dummy gate stack over the channel region of the fin such that sidewalls of the fin are covered by the dummy gate stack;

removing the second epitaxial layers from the source/drain region of the fin to form first gaps in the source/drain region;

after removing the second epitaxial layers from the source/drain region of the fin to form the first gaps in the source/drain region, forming a spacer layer on sidewalls of the dummy gate stack with a dielectric material while filling the first gaps with the dielectric material;

forming a third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the source/drain region to form a source/drain feature while the dielectric material fills the first gaps;

forming a dielectric layer over the source/drain feature;

removing the dummy gate stack from the channel region;

removing the second epitaxial layers from the channel region of the fin in the channel region to form second gaps; and

forming a gate stack over the channel region of the fin with a gate material, wherein the gate material fills the second gaps in the channel region.

14. The method of claim 13, wherein the device region is an n-type field effect transistor (NFET) region.

15. The method of claim 13, wherein the first composition comprises Si and the second composition comprises SiGe.

16. The method of claim 13, further comprising:

prior to forming the third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the source/drain region, performing an etch back to remove the dielectric material from the top surface and lateral surfaces of the stack of epitaxial layers and from top surface of the dummy gate stack.

17. The method of claim 13, further comprising:

prior to removing the dummy gate stack, performing a planarization process to expose top surface of the dummy gate stack.

18. A method comprising:

forming a fin in a device region over a substrate, the fin having a source/drain region and a channel region, the fin being formed of a stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition;

forming a dummy gate stack over a top surface and sidewalls of the fin in the channel region;

forming a third epitaxial layer on at least two surfaces of the stack of epitaxial layers in the source/drain region to form a source/drain;

performing a planarization process to expose top surfaces of the dummy gate stack;

removing the dummy gate stack from the channel region;

selectively removing a topmost first epitaxial layer over the channel region of the fin to expose a topmost second epitaxial layer; and

after selectively removing the topmost first epitaxial layer, forming a gate stack over the channel region of the fin, wherein the gate stack is disposed on sidewalls of the first and second epitaxial layers of the fin in the channel region and directly on the exposed topmost second epitaxial layer of the fin.

19. The method of claim 18, wherein the device region is a p-type field effect transistor (PFET) region, the first composition comprises Si, and the second composition comprises SiGe.

20. The method of claim 18, further comprising:

before forming the third epitaxial layer on at least two surfaces of the stack of epitaxial layers in the source/drain region to form the source/drain, selectively removing a topmost first epitaxial layer over the source/drain region to expose a topmost second epitaxial layer.