Semiconductor device and manufacturing method thereof

• US 9,899,405 B2
• Filed: 11/11/2015
• Issued: 02/20/2018
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Kim, Young Jae, Choi, Seung Woo, Yoo, Yong Min
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Jean Baptiste, Wilner
• Application Number:
  US14/938,180
• Publication Number:
  US 20160181273A1
• Time in Patent Office: 832 Days
• Field of Search: 438591
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

Claims

1. A manufacturing method of a semiconductor device, comprising:

forming a non-conductive layer to be perpendicular to a surface of a substrate in a trench of a structure in which a gate layer and an interlayer insulation layer are alternately stacked;

forming a channel layer to be perpendicular to the surface of the substrate at a lateral surface of the non-conductive layer;

repeating a first gas-supplying cycle for forming a barrier layer to be perpendicular to the surface of the substrate at a lateral surface of the channel layer wherein the first gas-supplying cycle includes, while supplying oxygen gas and a purge gas to a reactor during a first time, a second time, a third time, and a fourth time;

supplying a silicon source during the first time; and

activating the oxygen gas with plasma during the third time, and wherein the second gas-supplying cycle includes a first sub-gas-supplying cycle and a second sub-gas-supplying cycle, wherein, while supplying the oxygen gas and the purge gas to the reactor during a fifth time, a sixth time, a seventh time, an eighth time, a ninth time, and a tenth time, the first sub-gas-supplying cycle includes a step of supplying a silicon source gas during the fifth time without supplying the plasma and a step of stopping supplying of the silicon source gas during the sixth time, and the second sub-gas-supplying cycle includes a step of supplying phosphorous source gas during the seventh time and a step of supplying plasma during the ninth time; and

repeating a second gas-supplying cycle for forming a source layer, comprising one or more dopants, at a lateral surface of the barrier layer,

wherein the first gas-supplying cycle and the second gas-supplying cycle are performed by an atomic layer deposition method, and

wherein the one or more dopants diffuse through the barrier layer to the channel layer.

2. The manufacturing method of the semiconductor device of claim 1, wherein

a number of repetitions of the first sub-gas-supplying cycle and a number of repetitions of the second sub-gas-supplying cycle are different.

3. The manufacturing method of the semiconductor device of claim 1, further comprising

repeating a third gas-supplying cycle for forming a capping layer at a lateral surface of the source layer.

4. The manufacturing method of the semiconductor device of claim 3, wherein

the third gas-supplying cycle includes:

while supplying the oxygen gas and the purge gas to the reactor during an eleventh time, a twelfth time, a thirteenth time, and a fourteenth time,

supplying the silicon source during the eleventh time; and

activating the oxygen gas with the plasma during the thirteenth time.

5. The manufacturing method of the semiconductor device of claim 3, further comprising

performing heat treatment to the semiconductor device.

6. The manufacturing method of the semiconductor device of claim 4, wherein

conditions of the first gas-supplying cycle and the third gas-supplying cycle are different.

7. The manufacturing method of the semiconductor device of claim 6, wherein

the plasma powers supplied during the first gas-supplying cycle and the third gas-supplying cycle are different.

8. The manufacturing method of the semiconductor device of claim 6, wherein

the thickness of the films formed in the first gas-supplying cycle and the third gas-supplying cycle are different.

9. The manufacturing method of the semiconductor device of claim 1, further comprising

performing heat treatment to the semiconductor device to cause the one or more dopants to diffuse from the source layer to the channel layer.

10. The manufacturing method of the semiconductor device of claim 1, wherein

the forming of the channel layer includes forming the channel layer as a polysilicon layer.

11. A manufacturing method of a semiconductor device, comprising:

forming a non-conductive layer to be perpendicular to a surface of a substrate in a trench of a structure in which a gate layer and an interlayer insulation layer are alternately stacked;

forming a channel layer to be perpendicular to the surface of the substrate at a lateral surface of the non-conductive layer;

repeating a first gas-supplying cycle for forming a barrier layer to be perpendicular to the surface of the substrate at a lateral surface of the channel layer; and

repeating a second gas-supplying cycle for forming a source layer, comprising one or more dopants, at a lateral surface of the barrier layer,

wherein the first gas-supplying cycle and the second gas-supplying cycle are performed by an atomic layer deposition method, and

wherein the one or more dopants diffuse through the barrier layer to the channel layer,

wherein the first gas-supplying cycle includes,

while supplying oxygen gas and a purge gas to a reactor during a first time, a second time, a third time, and a fourth time;

supplying a silicon source during the first time; and

activating the oxygen gas with plasma during the third time,

repeating a third gas-supplying cycle for forming a capping layer at a lateral surface of the source layer, and

wherein the third gas-supplying cycle includes;

while supplying the oxygen gas and the purge gas to the reactor during an eleventh time, a twelfth time, a thirteenth time, and a fourteenth time,

supplying the silicon source during the eleventh time; and

activating the oxygen gas with the plasma during the thirteenth time.

12. The manufacturing method of the semiconductor device of claim 11, wherein conditions of the first gas-supplying cycle and the third gas-supplying cycle are different.

13. The manufacturing method of the semiconductor device of claim 12, wherein the plasma powers supplied during the first gas-supplying cycle and the third gas-supplying cycle are different.

14. The manufacturing method of the semiconductor device of claim 12, wherein the thickness of the films formed in the first gas-supplying cycle and the third gas-supplying cycle are different.

15. The manufacturing method of the semiconductor device of claim 11, further comprising performing heat treatment to the semiconductor device to cause the one or more dopants to diffuse from the source layer to the channel layer.

16. The manufacturing method of the semiconductor device of claim 11, further comprising performing heat treatment to the semiconductor device.

17. The manufacturing method of the semiconductor device of claim 11, wherein the forming of the channel layer includes forming the channel layer as a polysilicon layer.