Printable device wafers with sacrificial layers gaps

• US 9,899,432 B2
• Filed: 08/22/2016
• Issued: 02/20/2018
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher, Menard, Etienne, Meitl, Matthew, Carr, Joseph
• Primary Examiner(s): HENRY, CALEB E
• Application Number:
  US15/243,228
• Publication Number:
  US 20170133412A1
• Time in Patent Office: 547 Days
• Field of Search: 438700, 257E21214
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate

Abstract

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Claims

1. A wafer of devices comprising:

a substrate;

a sacrificial layer on the substrate, the sacrificial layer comprising an array of gaps;

at least one tether laterally extending from a sidewall of each gap in the array of gaps; and

an array of devices, each of the devices laterally attached to at least one respective tether such that each device is suspended within a respective gap of the array of gaps, wherein the tethers are at least partially in a common layer with at least a portion of the devices.

2. The wafer of claim 1, wherein each of the devices is secured above a bottom surface of the respective gap.

3. The wafer of claim 1, wherein the sacrificial layer comprises at least one material selected from a group consisting of molybdenum, aluminum, copper, nickel, chromium, tungsten, titanium and alloys thereof.

4. The wafer of claim 1, wherein each of the devices is an integrated circuit device.

5. The wafer of claim 1, wherein each of the devices is attached to the respective tether with an attachment area having a height that is less than a height of the device.

6. The wafer of claim 1, wherein each of the devices is thicker than the sacrificial layer.

7. The wafer of claim 1, wherein the respective tether is formed axially between adjacent devices of the array of devices.

8. The wafer of claim 1, wherein each of the devices is encapsulated by an inorganic capping layer and the capping layer is a metal or is amorphous silicon.

9. The wafer of claim 1, wherein one or more of the devices has a roughened surface that is encapsulated by an inorganic capping layer.

10. The wafer of claim 1, comprising:

one or more multi-layer electrical interconnect networks, each of the multi-layer electrical interconnect networks disposed on a semiconductor active layer of a corresponding device of the array of devices, wherein one or more of the multi-layer electrical interconnect networks is encapsulated by an inorganic capping layer.

11. The wafer of claim 1, wherein the substrate is an insulating substrate.

12. The wafer of claim 1, comprising:

a plurality of anchors disposed on the substrate and separated by the gaps, each of the anchors disposed adjacent to at least one device of the array of devices.

13. The wafer of claim 12, wherein at least one of the anchors is polysilicon.

14. The wafer of claim 12, wherein at least one of the anchors is ring shaped.

15. The wafer of claim 12, wherein at least one the anchors comprises a sidewall of a gap.

16. The wafer of claim 1, wherein the sacrificial layer is an electrically insulating layer.

17. A wafer of integrated circuit devices comprising:

a substrate;

a sacrificial layer on the substrate, the sacrificial layer comprising an array of gaps defining anchors separating the gaps;

at least one tether laterally extending from a sidewall of each anchor; and

an array of integrated circuit devices, each of the integrated circuit devices laterally attached to at least one respective tether such that each integrated circuit is suspended entirely over a respective gap of the array of gaps, wherein the tethers are at least partially in a common layer with at least a portion of the integrated circuit devices.

18. The wafer of claim 17, wherein each of the integrated circuit devices is attached to the respective tether with an attachment area having a height that is less than a height thereof.

19. The wafer of claim 17, wherein each of the integrated circuit devices is thicker than the sacrificial layer.