Semiconductor device having SOI substrate

• US 9,899,448 B2
• Filed: 03/09/2016
• Issued: 02/20/2018
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Arai, Yasuo, Okihara, Masao, Kasai, Hiroki
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/064,686
• Publication Number:
  US 20160190203A1
• Time in Patent Office: 713 Days
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claims

1. A photodiode-on-SOIS (silicon on insulator substrate) device, comprising:

a silicon on insulator (SOI) substrate that includes a first surface and a second surface opposite to the first surface;

a semiconductor layer that includes a third surface opposite to the first surface and a fourth surface opposite to the third surface, the fourth surface having a semiconductor element disposed thereon;

an oxide film layer that is formed in contact with the first surface and the third surface;

a first diffusion layer that is included in the semiconductor layer in a planar view, that is formed on a surface opposite to the third surface and that is connected to a reference potential, the oxide film layer being interposed between the surface opposite to the third surface and the third surface;

a photodiode, including;

a second diffusion layer that is connected to the reference potential and that is formed in a part of a region of the first surface corresponding to a region that is adjacent to the first diffusion layer in the planar view, and

a third diffusion layer that is formed in the part of the region of the first surface corresponding to the region that is adjacent to the first diffusion layer in the planar view, and that is formed separately from the second diffusion layer; and

a voltage application unit that applies a voltage to the second surface and the third diffusion layer in order to form a depletion layer for the photodiode in the SOI substrate.

2. The photodiode-on-SOIS device according to claim 1, wherein:

the SOI substrate and the third diffusion layer are of a first conductivity type; and

the second diffusion layer is of a second conductivity type that is opposite in conductivity type to the first conductivity type.

3. The photodiode-on-SOIS device according to claim 1, further comprising:

a first electrode that passes through the oxide film layer and is connected to the first diffusion layer;

a second electrode that passes through the oxide film layer and is connected to the second diffusion layer; and

a third electrode that passes through the oxide film layer and is connected to the third diffusion layer, wherein;

the first diffusion layer is connected to the reference potential via the first electrode;

the second diffusion layer is connected to the reference potential via the second electrode; and

the third diffusion layer is connected to the voltage application unit via the third electrode.

4. The photodiode-on-SOIS device according to claim 1, wherein the semiconductor element has a channel region within the semiconductor layer.

5. The photodiode-on-SOIS device according to claim 1, wherein the voltage application unit applies the voltage that forms the depletion layer to the entire SOI substrate.

6. The photodiode-on-SOIS device according to claim 1, wherein the first diffusion layer that is connected to the reference potential prevents the voltage applied by the voltage application unit from reaching a boundary between the third surface of the semiconductor layer and the oxide film layer.

7. A photodiode-on-SOIS (silicon on insulator substrate) device, comprising:

a semiconductor layer having a first surface and a second surface opposite to the first surface;

a diffusion layer formed in the semiconductor layer at the first surface thereof;

an oxide film layer formed on the first surface of the semiconductor layer to cover the semiconductor layer and the diffusion layer;

a semiconductor element formed on the oxide film layer and directly above the diffusion layer;

a first extraction electrode region formed in the diffusion layer; and

a photodiode, including;

a second extraction electrode region formed in the semiconductor layer and not in the diffusion layer, and

a third extraction electrode region formed in the semiconductor layer and not in the diffusion layer, the second and third extraction electrode region being of different semiconductor types, wherein

a reference potential is applicable to the second surface of the semiconductor layer, the first extraction electrode region and the third extraction electrode region, so as to form a depletion layer for the photodiode.