Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
First Claim
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1. A semiconductor device comprising:
- a semiconductor substrate; and
a plurality of field effect transistors (FETs) on the semiconductor substrate and each comprisinga gate,spaced apart source and drain regions on opposite sides of the gate,upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,a halo implant having a peak halo dopant concentration of at least 1×
1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, anda second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×
1019 atoms/cm3.
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Abstract
A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.
213 Citations
21 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate; and a plurality of field effect transistors (FETs) on the semiconductor substrate and each comprising a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions, a halo implant having a peak halo dopant concentration of at least 1×
1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, anda second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×
1019 atoms/cm3. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor device comprising:
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a semiconductor substrate; and a plurality of CMOS transistors on the semiconductor substrate and each comprising a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions, a halo implant having a peak halo dopant concentration of at least 1×
1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, anda second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×
1019 atoms/cm3;the upper and lower superlattice layers each comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of making a semiconductor device comprising:
forming a plurality of field effect transistors (FETs) on a semiconductor substrate, each comprising a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions, a halo implant having a peak halo dopant concentration of at least 1×
1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, anda second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×
1019 atoms/cm3.- View Dependent Claims (17, 18, 19, 20, 21)
Specification