Thin film transistor substrate, method of manufacturing the same, and display apparatus having the same

• US 9,899,531 B2
• Filed: 05/13/2015
• Issued: 02/20/2018
• Est. Priority Date: 08/05/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yoon, Seungho, Kim, Bong-Kyun, Kim, Youngjun, Park, Hongsick, Kim, Byeong-Beom, Shin, Sangwon
• Primary Examiner(s): Nguyen, Thanh-Nhan P
• Application Number:
  US14/710,739
• Publication Number:
  US 20160043226A1
• Time in Patent Office: 1,014 Days
• Field of Search: 349 43, 438104, 257 43
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A thin film transistor substrate includes a thin film transistor including a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Each of the source electrode and the drain electrode includes a wire layer and a protective layer. The protective layer includes zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight.

Claims

1. A method of manufacturing a thin film transistor substrate, comprising:

forming a gate electrode of a thin film transistor on a base substrate;

sequentially forming a semiconductor material layer, a barrier material layer, a metal material layer and a protective material layer on the base substrate and the gate electrode, each of the material layers on the base substrate and the gate electrode insulated from the gate electrode, the protective material layer comprising zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight;

forming a first photoresist layer pattern on the protective material layer on the base substrate and the gate electrode;

selectively etching the semiconductor material layer, the barrier material layer, the metal material layer and the protective material layer using the first photoresist layer pattern as a mask to form a first structure comprising a semiconductor pattern, a barrier pattern, a wire pattern and a protective pattern, respectively;

removing a portion of the first photoresist layer pattern on the semiconductor pattern, the barrier pattern, the wire pattern and the protective pattern to form a second photoresist layer pattern via which a portion of the first structure is exposed at a channel area of the thin film transistor; and

etching the semiconductor pattern, the barrier pattern, the wire pattern and the protective pattern at the channel area of the thin film transistor using the second photoresist layer pattern as a mask to form a second structure comprising a semiconductor layer, a barrier layer, a wire layer and a protective layer of the thin film transistor, respectively.

2. The method of claim 1, wherein the first structure is formed using a first etchant which etches the semiconductor material layer, the barrier material layer, the metal material layer and the protective material layer.

3. The method of claim 1, wherein the second structure is formed using a second etchant which etches the semiconductor pattern, the barrier pattern, the wire pattern and the protective pattern at the exposed portion of the first structure.

4. The method of claim 1, wherein the semiconductor layer comprises an oxide semiconductor material, the oxide semiconductor material comprising an oxide material of at least one of zinc (Zn), indium (In), gallium (Ga) and tin (Sn).

5. The method of claim 1, wherein the etching the barrier material layer, the metal material layer and the protective material layer using the first photoresist layer pattern as the mask forms inclined sides of the barrier layer, the wire layer and the protective layer of the thin film transistor, respectively, the inclined sides being aligned with each other.