Process for preparing a semiconductor structure for mounting

• US 9,899,578 B2
• Filed: 08/14/2015
• Issued: 02/20/2018
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Inventors: Sun, Decai, Sun, Charlene, Shchekin, Oleg
• Primary Examiner(s): Zarneke, David
• Application Number:
  US14/826,473
• Publication Number:
  US 20150349217A1
• Time in Patent Office: 921 Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2933/005 relating to encapsulations
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01L 33/54 having a particular shape
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

Claims

1. A device comprising:

a semiconductor structure comprising;

a light emitting layer disposed between an n-type region and a p-type region;

a plurality of voids extending into the n-type region, the light emitting layer, and the p-type region of the semiconductor structure;

an n-electrode metal disposed in the plurality of voids, wherein the n-electrode metals extends to an edge of the device;

a reflective metal disposed on the p-type region;

a p-electrode metal disposed on the reflective metal; and

a support material disposed in the plurality of voids, wherein a surface of the device is planar, wherein the planar surface of the device includes a surface of the support material, a surface of the n-electrode metal, and a surface of the p-electrode metal.

2. The device of claim 1, further comprising:

a trench disposed between the n-electrode metal and the p-electrode metal, wherein the trench is filled with the support material.

3. The device of claim 1 wherein the support material comprises one of a polyimide material, a benzocyclobutene material, a material comprising polyimide and epoxy, and a material comprising polyimide and silicone.

4. The device of claim 1 wherein the support material is sufficiently solid to support the semiconductor structure when mounted to a carrier.

5. The device of claim 1 wherein the support material has a glass transition temperature greater than an operating temperature of the semiconductor structure.

6. The device of claim 1 wherein the support material has a glass transition temperature of at least 195 degrees Celsius.

7. The device of claim 1 wherein the support material acts as a passivation layer, the passivation layer being operable to prevent contamination of the semiconductor structure.

8. The device of claim 1 further comprising:

a carrier, wherein the semiconductor structure is mounted to the carrier via the planar surface such that the support material bears upon a portion of the carrier to permit the support material to further support the semiconductor structure.

9. The device of claim 1 wherein the support material has a thermal expansion coefficient sufficiently similar to a thermal expansion coefficient of the n-electrode metal and the p-electrode metal, such that thermal induced stresses in the semiconductor structure are minimized when a temperature of the semiconductor structure changes.

10. The device of claim 1 wherein a portion of the n-electrode metal that extends to an edge of the device is disposed over a portion of the reflective metal.

11. The device of claim 1 wherein the p-electrode metal is disposed in a center of the device between two portions of the n-electrode metal that extend to first and second edges of the device.

12. The device of claim 1 further comprising:

a plurality of metal bonding members deposited on the n-electrode metal and the p-electrode metal; and

an additional support material disposed in a space between the plurality of metal bonding members.

13. The device of claim 12 wherein the additional support material is recessed with respect to an outer surface of the plurality of metal bonding members.

18. The device of claim 1 wherein the plurality of voids extend through the p-type region and the light emitting layer and end in the n-type region, such that the plurality of voids do not extend through an entire thickness of the semiconductor structure.

14. A method comprising:

forming a plurality of voids extending into an n-type region, a light emitting layer, and a p-type region of a semiconductor structure in a device, wherein the light emitting layer is disposed between the n-type region and the p-type region;

disposing an n-electrode metal in the plurality of voids, wherein the n-electrode metal extends to an edge of the device;

disposing a reflective metal on the p-type region;

disposing a p-electrode metal on the reflective metal;

disposing a support material in the plurality of voids; and

forming a planar surface of the device, wherein the planar surface of the device includes a surface of the support material, a surface of the n-electrode metal, and a surface of the p-electrode metal.

15. The method of claim 14, further comprising:

forming a trench between the n-electrode metal and the p-electrode metal; and

filling the trench with the support material.

16. The method of claim 14 wherein the support material comprises one of a polyimide material, a benzocyclobutene material, a material comprising polyimide and epoxy, and a material comprising polyimide and silicone.

17. The method of claim 14, further comprising:

mounting the semiconductor structure on a carrier such that the support material is in contact with the carrier.