Master-slave multi-phase charging
First Claim
Patent Images
1. A charging circuit, comprising:
- a control terminal;
a clock terminal;
a high-side field-effect transistor (FET) and a low-side FET;
a pulse width modulated (PWM) driver to drive the high-side FET and the low-side FET;
feedback circuitry to generate a control signal;
a clock module comprising a clock generator and a delay element, the clock module to generate a clock signal that is provided to the PWM driver; and
a selection module to configure the charging circuit in a first configuration or a second configuration,wherein in the first configuration, the control signal is provided to the PWM driver and to the control terminal, and the clock signal is provided from an output of the clock generator,wherein in the second configuration, an externally generated control signal received on the control terminal is provided to the PWM driver, an externally generated clock signal received on the clock terminal is provided to the delay element, and the clock signal is provided from an output of the delay element.
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Abstract
A multi-phase charging circuit comprises a device that can be configured for master mode operation or slave mode operation. In master mode operation, the device generates a control signal and a clock signal to control operation of a switching circuit for generating charging current. In slave mode operation, the device receives externally generated control and clock signals to control operation of its switching circuit.
43 Citations
20 Claims
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1. A charging circuit, comprising:
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a control terminal; a clock terminal; a high-side field-effect transistor (FET) and a low-side FET; a pulse width modulated (PWM) driver to drive the high-side FET and the low-side FET; feedback circuitry to generate a control signal; a clock module comprising a clock generator and a delay element, the clock module to generate a clock signal that is provided to the PWM driver; and a selection module to configure the charging circuit in a first configuration or a second configuration, wherein in the first configuration, the control signal is provided to the PWM driver and to the control terminal, and the clock signal is provided from an output of the clock generator, wherein in the second configuration, an externally generated control signal received on the control terminal is provided to the PWM driver, an externally generated clock signal received on the clock terminal is provided to the delay element, and the clock signal is provided from an output of the delay element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A charging circuit, comprising:
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means for driving a high side field effect transistor (FET) and a low side FET in response to a control signal and a clock signal; means for generating a clock signal when the charging circuit is in a first configuration; means for generating the clock signal by delaying an externally received clock signal when the charging is in a second configuration; means for generating a control signal when the charging circuit is in the first configuration; means for receiving the control signal externally when the charging circuit is in the second configuration; and means for selecting between the first configuration and the second configuration. - View Dependent Claims (17, 18, 19, 20)
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Specification