Phase interpolators and push-pull buffers
First Claim
Patent Images
1. An apparatus comprising:
- a first buffer configured to receive a first clock signal having a first phase from a first push-pull buffer;
a second buffer configured to receive a second clock signal having a second phase from the first push-pull buffer;
a third buffer configured to receive a third clock signal having a third phase from a second push-pull buffer;
a fourth buffer configured to receive a fourth clock signal having a fourth phase from the second push-pull buffer; and
a controller configured to selectively activate the first buffer or second buffer based on a select signal and to selectively activate the third buffer or fourth buffer based on the select signal, wherein outputs of the first, second, third, and fourth buffers are coupled together to provide an output signal.
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Abstract
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.
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Citations
20 Claims
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1. An apparatus comprising:
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a first buffer configured to receive a first clock signal having a first phase from a first push-pull buffer; a second buffer configured to receive a second clock signal having a second phase from the first push-pull buffer; a third buffer configured to receive a third clock signal having a third phase from a second push-pull buffer; a fourth buffer configured to receive a fourth clock signal having a fourth phase from the second push-pull buffer; and a controller configured to selectively activate the first buffer or second buffer based on a select signal and to selectively activate the third buffer or fourth buffer based on the select signal, wherein outputs of the first, second, third, and fourth buffers are coupled together to provide an output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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11. A method comprising:
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receiving, at a first buffer, a first clock signal having a first phase from a first push-pull buffer; receiving at a second buffer a second clock signal having a second phase from the first push-pull buffer; selecting, by a controller, the first or second clock signals; receiving at a third buffer a third clock signal having a third phase from a second push-pull buffer; receiving at a fourth buffer a fourth clock signal having a fourth phase from the second push pull buffer; selecting, by the controller, the third or fourth clock signals; and interpolating the selected first or second clock signal and the selected third or fourth clock signal to provide an output signal.
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Specification