RF circuit with switch transistor with body connection

• US 9,900,001 B2
• Filed: 04/23/2015
• Issued: 02/20/2018
• Est. Priority Date: 03/06/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Aubain, Max Samuel, Kemerling, Clint
• Primary Examiner(s): Chen, Sibin
• Application Number:
  US14/694,707
• Publication Number:
  US 20160261265A1
• Time in Patent Office: 1,034 Days
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/30 Modifications for providing a predetermined threshold before switching shaping pulses by thresholding H03K5/08
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/01 Details

Abstract

In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.

Claims

1. A method comprising:

in a switching circuit, passing a Radio Frequency (RF) electrical signal from a first RF signal node to a second RF signal node through a first switch during an on state of the first switch, wherein the first switch includes a plurality of N-channel transistors coupling the first RF signal node to the second RF signal node, each of the transistors having a source, a drain, a gate, and a body;

during the on state of the first switch, applying a gate control voltage to respective gates of the transistors; and

during the on state of the first switch, applying a positive control bias to the respective bodies of the transistors, further wherein the positive control bias is greater than a built-in voltage of a p-n junction of the transistors, wherein the plurality of transistors are coupled source to drain from the first RF signal node to ground;

further wherein applying the gate control voltage and applying the positive control bias comprises producing the gate control voltage and the positive control bias as a single control voltage that is applied through a first resistance to the gates of the transistors and through a second resistance to the bodies of the transistors, wherein the first resistance is different from the second resistance; and

wherein the first resistance and the second resistance share a common circuit node.

2. The method of claim 1, further comprising:

applying a negative control bias to the respective bodies of the transistors during an off state of the first switch.

3. The method of claim 1, further comprising:

decoding control signals to produce decoded signals;

passing the decoded signals to a level shifter;

generating the single control voltage at the level shifter based on the decoded signals;

generating the gate control voltage and the positive control bias from the control voltage.

4. A Radio Frequency (RF) circuit comprising:

a first N-channel transistor;

a second N-channel transistor, wherein the first N-channel transistor and the second N-channel transistor are coupled source to drain from a RF signal node to ground;

a gate control voltage input coupled with gate terminals of the first N-channel transistor and second N-channel transistor, the gate control voltage input configured to apply a gate control voltage;

a body control voltage input coupled with a body terminal of the first N-channel transistor and a body terminal of the second N-channel transistor, the body control voltage input configured to apply a body control voltage, wherein the body control voltage is a positive bias voltage when the first N-channel transistor and second N-channel transistor are in an on state, further wherein the positive bias voltage is greater than a built-in voltage of a p-n junction of each of the first N-channel transistor and second N-channel transistors;

a voltage control source that produces the gate control voltage and the body control voltage as a single control voltage that is applied through a first resistance to the gate terminals of the first N-channel transistor and second N-channel transistor and through a second resistance to the body terminals of the first N-channel transistor and second N-channel transistor;

wherein the first resistance is different from the second resistance; and

wherein the first resistance and the second resistance share a common circuit node.

5. The RF circuit of claim 4, wherein:

the positive bias voltage when the first N-channel transistor and second N-channel transistor are in the on state is greater than about 0.7 volts.

6. The RF circuit of claim 4, wherein:

the positive bias voltage improves device linearity of the RF circuit when the first N-channel transistor and second N-channel transistor are in the on state.

7. The RF circuit of claim 6, wherein:

the improved device linearity is a mitigated harmonic signal.

8. The RF circuit of claim 7, wherein:

the harmonic signal is at three times a fundamental frequency of the RF circuit.

9. The RF circuit of claim 6, wherein:

the improved device linearity is a mitigated intermodulation distortion.

10. The RF circuit of claim 4, wherein the second resistance comprises:

a first resistor in series with the body terminal of the first N-channel transistor and coupled between the body control voltage input and the body terminal of the first N-channel transistor; and

a second resistor in series with the body terminal of the second N-channel transistor and coupled between the body control voltage input and the body terminal of the second N-channel transistor.

11. The RF circuit of claim 4, wherein the voltage control source comprises:

a positive voltage generator;

a negative voltage generator; and

a voltage level shifter configured to operate under control of the positive voltage generator and the negative voltage generator.