Digital driving of active matrix displays

• US 9,905,159 B2
• Filed: 10/30/2013
• Issued: 02/27/2018
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International, Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno
• Inventors: Genoe, Jan
• Primary Examiner(s): Lee, Nicholas J
• Assistant Examiner(s): Taylor, Jr., Duane N
• Application Number:
  US14/440,219
• Publication Number:
  US 20150302795A1
• Time in Patent Office: 1,581 Days
• Field of Search: None
• CPC Class Codes: G02F 1/13 based on liquid crystals, e.g. single liquid crystal display cells
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2025 the sub-frames having all the same time duration
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A method for digital driving of an active matrix display with a predetermined frame rate is described. The display contains a plurality of pixels organized in a plurality of rows and a plurality of columns. The method includes representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital image code. The method also includes dividing the image frame into sub-frames, which may be of substantially equal duration. Within each sub-frame, the method includes sequentially selecting at least one of the plurality of rows twice. Upon a first selection, a first digital code is written to the selected row and upon a second selection a second digital code is written to the selected row. There is a predetermined time delay between the second selection and the first selection. Digital driving circuitry is also described.

Claims

1. A method for digital driving of an active matrix display with a predetermined frame rate, the display comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, the method comprising:

representing each of a plurality of pixels of an image to be displayed within an image frame by an n-bit digital image code;

dividing the image frame into a natural number of sub-frames;

within each sub-frame of a respective image frame, sequentially selecting at least two or more of the plurality of rows twice, wherein sequentially selecting a row includes a sequential first selection and second selection of the row, wherein upon the first selection a first digital code is written to the selected row and upon the second selection a second digital code is written to the selected row, there being a predetermined time delay between the second selection and the first selection, wherein the first digital code and the second digital code are written respectively by driving the first digital code and the second digital code using pulse-width modulation, and wherein the first digital code corresponds to a first predetermined bit of the n-bit digital image code and the second digital code corresponds to a second predetermined bit of the n-bit image code.

2. The method according to claim 1, wherein dividing the image frame comprises dividing the image frame into sub-frames of equal duration.

3. The method according to claim 1, wherein the second selection of the plurality of rows takes place for at least 35% of the sub-frames.

4. The method according to claim 3, wherein the second selection of the plurality of rows takes place for all but the last few sub-frames.

5. The method according to claim 1, wherein dividing the image frame into sub-frames comprises dividing the image frame into N sub-frames, wherein N is equal to n.

6. The method according to claim 1, wherein n is not a natural power of two, wherein dividing the image frame into sub-frames comprises dividing the image frame into N sub-frames, wherein N is a power of 2 superior and closest to n.

7. The method according to claim 1, wherein each sub-frame is further divided into time slots.

8. The method according to claim 7, further comprising assigning a number of time slots to each bit of the n-bit digital image code according to each bit significance in the code.

9. The method according to claim 8, wherein each sub-frame is further divided into 2ⁿ/N time slots.

10. The method according to claim 1, wherein a time delay between the second selection and the first selection in a x^th sub-frame corresponds to ½

<sup>N−

x</sup> of the sub-frame duration.

11. The method according to claim 10, further comprising assigning 2^m−

1 time slots to the m^th bit of the n-bit image code.

12. The method according to claim 1, wherein the time delay between the second selection and the first selection in a sub-frame within one frame is not smaller than the time delay between the second selection and the first selection in an earlier sub-frame within the one frame.

13. The method according to claim 1, wherein the number of bits used per image color (n-bit gray scale) is 8.

14. Digital driving circuitry for driving, with a predetermined frame rate, an active matrix display that includes a plurality of pixels logically organized in a plurality of rows and a plurality of columns, so as to display subsequent frames of an image to be displayed, the image being represented by an n-bit digital image code for each pixel to be displayed within an image frame, and the image frame being divided into a natural number of sub-frames, the digital driving circuitry comprising:

digital select line driving circuitry configured to sequentially select the plurality of rows; and

digital data line driving circuitry configured to write the digital image code to corresponding pixels in a selected row;

wherein the digital select line driving circuitry is further configured to sequentially select, within each sub-frame of a respective image frame, at least two or more of the plurality of rows twice, so as to, upon a first selection, write a first digital code to the selected row and, upon a sequential second selection, write a second digital code to the selected row, there being a predetermined time delay between the second selection and the first selection, wherein the first digital code and the second digital code are written respectively by driving the first digital code and the second code using pulse-width modulation, and wherein the first digital code corresponds to a first predetermined bit of the n-bit digital image code and the second digital code corresponds to a second predetermined bit of the n-bit digital image code.

15. The digital driving circuitry according to claim 14, wherein the digital select line driving circuitry further comprises a time delay determination circuit for determining the predetermined time delay between the second selection and the first selection.

16. The digital driving circuitry according to claim 15, wherein the time delay determination circuit comprises a shift register.

17. An active matrix display comprising an array of light emitting elements arranged for being driven by the digital driving circuitry according to claim 16.

18. The active matrix display according to claim 17, wherein the active matrix display is an active matrix organic light emitting diode (AMOLED) display.

19. The active matrix display according to claim 18, wherein the light emitting elements are any of fluorescent organic light emitting diodes (OLEDs), phosphorescent OLEDs, light emitting polymers, or polydendrimers.