Semiconductor module with bus bar including stacked wiring layers

• US 9,905,541 B2
• Filed: 03/26/2015
• Issued: 02/27/2018
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Ishino, Hiroshi, Watanabe, Tomokazu
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): CROSS, XIA L
• Application Number:
  US15/129,860
• Publication Number:
  US 20170148770A1
• Time in Patent Office: 1,069 Days
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/29034 the layer connector covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/3735 : Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/492 : Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: H02M 7/5387 : in a bridge configuration
• CPC Class Codes: H02P 27/06 : using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

A semiconductor module includes upper arms and lower arms for three phases, heat sinks, a main circuit side bus bar, an output terminal side bus bar, a control terminal, and a resin mold portion. The output terminal side bus bar includes U-phase to W-phase wiring layers disposed opposite to each other via an insulating layer and U to W terminals electrically connecting each of the U-phase to W-phase wiring layer and a load. A stacked layer number of the U-phase to W-phase wiring layer is set to be an even number.

Claims

1. A semiconductor module comprising:

upper arms and lower arms for three phases, each of the upper arms and the lower arms including a semiconductor chip in which a semiconductor switching element is formed, the semiconductor chip having a front surface and a rear surface;

heat sinks respectively disposed to the front surface and the rear surface of the semiconductor chip in each of the upper arms and the lower arms;

a main circuit side bus bar forming a main circuit that includes a positive electrode wiring layer connected to positive electrode sides of the semiconductor chips in the upper arms, a positive electrode terminal for electrically connecting the positive electrode wiring layer and a positive electrode side of an external power source, a negative electrode wiring layer disposed opposite to the positive electrode wiring layer via an insulating layer and connected to negative electrode sides of the semiconductor chips in the lower arms, and a negative electrode terminal for electrically connected with the negative electrode wiring layer;

an output terminal side bus bar including an output wiring layer connected to negative electrode sides of the semiconductor chips in the upper arms and positive electrode sides of the semiconductor chips in the lower arms so as to be connected to middle potential points of the upper arms and the lower arms and an output terminal electrically connecting the output wiring layer and a load;

a control terminal that becomes a signal line of the semiconductor switching elements; and

a resin mold portion covering the upper arms and the lower arms while exposing one surface of each of the heat sinks, an end portion of the main circuit bus bar adjacent to the positive electrode terminal and the negative electrode terminal, an end portion of the output terminal side bus bar adjacent to the output terminal, and an end portion of the control terminal, wherein

the output wiring layer includes a U-phase wiring layer, a V-phase wiring layer, and a W-phase wiring layer electrically connected with the middle potential point of the upper arm and the lower arm in each of the three phases, the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer are stacked vertically and imbedded in an insulating layer and are electrically insulated from each other via the insulating layer being interposed between each of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer,

the output terminal includes a U terminal, a V terminal, and a W terminal electrically connecting each of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer and the load, and

a stacked layer number of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer is set to be an even number.

2. The semiconductor module according to claim 1, wherein

the output terminal side bus bar and the main circuit side bus bar are integrated into a multilayer wiring bus bar.

3. The semiconductor module according to claim 2, wherein

a stacked layer number of the positive electrode wiring layer and the negative electrode wiring layer is same as the stacked layer number of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer.

4. The semiconductor module according to claim 2, wherein

the stacked layer number of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer is four, and one of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer is divided into two layers.

5. The semiconductor module according to claim 4, wherein

another of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer is disposed between the one of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer divided into two layers.

6. The semiconductor module according to claim 2, wherein

the end portion of the main circuit bus bar adjacent to the positive electrode terminal and the negative electrode terminal and the end portion of the output terminal side bus bar adjacent to the output terminal are exposed from opposed sides of the resin mold portion.

7. The semiconductor module according to claim 6, wherein

the resin mold portion has a quadrangular plate shape, the end portion of the main circuit side bus bar adjacent to the positive electrode terminal and the negative electrode terminal and the end portion of the output terminal side bus bar adjacent to the output terminal are exposed from two opposed sides of the resin mold portion, and an end portion of the control terminal in the upper arms and an end portion of the control terminal in the lower arms are exposed from the other two opposed sides of the resin mold portion.

8. The semiconductor module according to claim 2, wherein

each of the U-phase wiring layer, the V-phase wiring layer, and the W-phase wiring layer is designed so that a width is larger than a thickness.

9. The semiconductor module according to claim 2, wherein

the semiconductor chips in the upper arms and the semiconductor chips in the lower arms are arranged so that the front surfaces face a same direction and the rear surfaces face a same direction, and the multilayer wiring layer bus bar is disposed to pass between the semiconductor chips in the upper arms and the semiconductor chips in the lower arms.

10. The semiconductor module according to claim 9, wherein

the multilayer wiring bus bar is formed of a plate-shaped and rod-shaped member extending from the end portion adjacent to the positive electrode terminal and the negative electrode terminal toward the output terminal, and in a width direction that intersects a longitudinal direction of the multilayer wiring bus bar,

on one surface of the multilayer wiring bus bar, a first output electrode electrically connected with front surface electrodes disposed to the front surfaces of the semiconductor chips in the upper arms and the output wiring layer, and a negative electrode electrically connected with front surface electrodes disposed to the front surfaces of the semiconductor chips in the lower arms and the negative electrode wiring layer are formed,

on the other surface opposite from the one surface of the multilayer wiring bus bar, a positive electrode electrically connected with rear surface electrodes disposed to the rear surfaces of the semiconductor chips in the upper arms and the positive electrode wiring layer, and a second output electrode connected with rear surface electrodes disposed to the rear surfaces of the semiconductor chips in the lower arms and the output wiring layer are formed, and

in a cross section cutting the multilayer wiring bus bar formed into the plate-shaped and rod-shaped member in the width direction, the first output electrode and the second output electrode are disposed on one diagonal and are electrically connected in the multilayer wiring bus bar, and the positive electrode and the negative electrode are disposed on the other diagonal.