Memory cell comprising first and second transistors and methods of operating

• US 9,905,564 B2
• Filed: 02/15/2013
• Issued: 02/27/2018
• Est. Priority Date: 02/16/2012
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductors, Inc.
• Inventors: Widjaja, Yuniarto, Han, Jin-Woo, Louie, Benjamin S.
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US14/380,779
• Publication Number:
  US 20150023105A1
• Time in Patent Office: 1,838 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/70 Bipolar devices
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Claims

1. A semiconductor memory cell comprising:

a bi-stable floating body transistor comprising a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and

an access device;

wherein said bi-stable floating body transistor and said access device are electrically connected in series.

2. The semiconductor memory cell of claim 1, wherein said access device comprises a metal-oxide-semiconductor transistor.

3. The semiconductor memory cell of claim 2, wherein said access transistor is of the same conductivity type as said bi-stable floating body transistor.

4. The semiconductor memory cell of claim 2, wherein said access transistor has a conductivity type different from a conductivity type of said bi-stable floating body transistor.

5. The semiconductor memory cell of claim 1, wherein said bi-stable floating body transistor comprises a buried well region.

6. A semiconductor memory cell comprising:

a first transistor having a floating body;

a buried layer below said floating body, wherein application of voltage on said buried layer maintains a state of said memory cell; and

a second transistor;

wherein said first transistor having a floating body transistor comprises a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and

wherein said first and second transistors are connected in series.

7. A semiconductor memory cell comprising:

a bi-stable floating body transistor; and

a floating gate transistor;

wherein said bi-stable floating body transistor comprises a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.

8. A semiconductor memory cell comprising:

a first bi-stable floating body transistor; and

a second bi-stable floating body transistor;

wherein said first and second floating body transistors are configured to store complementary charges; and

wherein both said first bi-stable floating body transistor and said second bi-stable floating body transistor comprise a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.

9. A semiconductor memory cell comprising:

a first transistor having a first body;

a second transistor having a second body;

a substrate underlying both of said first and second bodies;

a buried layer interposed between said substrate and at least one of said first and second bodies;

a first source region contacting said first body;

a first drain region separated from said first source line region and contacting said first body;

a first gate insulated from said first body;

an insulating member insulating said first body from said second body;

a second source region contacting said second body;

a second drain region separated from said second source region and contacting said second body; and

a second gate insulated from said second body;

wherein said first body is a floating body and said second body is a well region electrically connected to said buried layer;

wherein said first body has a first conductivity type selected from p-type conductivity type and n-type conductivity type;

wherein said second body has a second conductivity type selected from said p-type conductivity type and n-type conductivity type; and

wherein said first conductivity type is different from said second conductivity type.

10. The semiconductor memory cell of claim 9, wherein said first gate is positioned between said first source region and said first drain region and said second gate is positioned between said second source region and said second drain region.

11. The semiconductor memory cell of claim 9, wherein said first transistor is a floating body transistor and said second transistor is an access transistor.

12. The semiconductor memory cell of claim 9, wherein said first body is a floating body and said second body is a well region electrically connected to said substrate.

13. The semiconductor memory cell of claim 9, wherein said first body has a first conductivity type selected from p-type conductivity type and n-type conductivity type, wherein said second body has said first conductivity type, and wherein said first and second source regions and first and second drain regions each have a second conductivity type selected from said p-type conductivity type and n-type conductivity type, and wherein said first conductivity type is different from said second conductivity type.

14. A semiconductor memory cell comprising:

a first transistor having a first body;

a second transistor having a second body;

a substrate underlying both of said first and second bodies;

a buried layer interposed between said substrate and at least one of said first and second bodies;

a first source region contacting said first body;

a first drain region separated from said first source line region and contacting said first body;

a first gate insulated from said first body;

an insulating member insulating said first body from said second body;

a second source region contacting said second body;

a second drain region separated from said second source region and contacting said second body; and

a second gate insulated from said second body;

wherein said semiconductor memory cell comprises a reference cell, said reference cell further comprising;

a sense line region spaced apart from said first source region and said first drain region and contacting said first body, wherein said first body has a first conductivity type selected from p-type conductivity type and n-type conductivity type, and wherein said sense line region has said first conductivity type.