Variable resistance memory

• US 9,905,611 B2
• Filed: 03/09/2016
• Issued: 02/27/2018
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Ueda, Yoshihiro
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US15/065,506
• Publication Number:
  US 20170077175A1
• Time in Patent Office: 720 Days
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions.

Claims

1. A variable resistance memory comprising:

first and second diffusion regions provided in first and second semiconductor regions of a semiconductor layer, respectively;

a first memory cell provided on the first diffusion region, the first memory cell including a first transistor and a first memory element, the first transistor having a first gate connected to a word line, and the word line extending in a first direction parallel to a surface of the semiconductor layer; and

a second transistor provided on the second diffusion region and connected to one end of the first memory cell via a first bit line, the first bit line extending in a second direction parallel to the surface of the semiconductor layer, and the second direction intersecting the first direction,

wherein;

the second semiconductor region extends in a third direction parallel to the surface of the semiconductor layer, and the third direction extends between the first and second directions in a same plane and intersects the first and second directions,

the first transistor includes a first semiconductor portion extending in a fourth direction perpendicular to the surface of the semiconductor layer,

the first gate is provided on a first gate insulating film on a side face in the second direction of the first semiconductor portion,

a first terminal of the first transistor is provided on a side of the first diffusion region of the first semiconductor portion,

a second terminal of the first transistor is provided on an opposite side of the first terminal in the fourth direction of the first semiconductor portion,

the memory element is provided above the first semiconductor portion in the fourth direction and connected to the second terminal,

the second transistor includes a second semiconductor portion extending in the fourth direction,

a gate of the second transistor is provided on a second gate insulating film on the side face in the second direction of the second semiconductor portion,

a third terminal of the second transistor is provided on the side of the second diffusion region of the second semiconductor portion,

a fourth terminal of the second transistor is provided on the opposite side of the third terminal in the fourth direction of the second semiconductor portion, and

the fourth terminal is connected to the first bit line.

2. The memory of claim 1, wherein a longitudinal direction of the second diffusion region is along the third direction.

3. The memory of claim 1, further comprising:

a second memory cell provided on the first diffusion region, the second memory cell including a third transistor and a second memory element, and the third transistor having a second gate connected to the word line; and

a fourth transistor provided on the second diffusion region and connected to one end of the second memory cell via a second bit line, the second bit line extending in the second direction,

wherein;

the second memory cell is adjacent to the first memory cell in the first direction and the second memory cell is connected to the first memory cell via a portion extending in the first direction of the first diffusion region, and

the fourth transistor is adjacent to the second transistor in the third direction and the third transistor is connected to the second transistor via the second diffusion region.

4. The memory of claim 3, further comprising:

a source line connected to the other end of the first memory cell and the other end of the second memory cell,

wherein the source line is provided in the first diffusion region.

5. The memory of claim 3, further comprising:

a first interconnect extending in the first direction and connected to the gate of the second transistor; and

a second interconnect extending in the first direction and connected to a gate of the fourth transistor, the second interconnect being adjacent to the first interconnect in the second direction.

6. The memory of claim 1, further comprising:

a fifth transistor provided on the first diffusion region and connected to the other end of the first memory cell via a source line,

wherein the source line is provided in the first diffusion region.

7. The memory of claim 1, wherein:

a first dimension in the first direction of the second semiconductor portion is larger than a second dimension in the first direction of the first semiconductor portion.

8. The memory of claim 1, wherein an insulating film is provided between the first diffusion region and the second diffusion region.

9. A variable resistance memory comprising:

a first diffusion region in a first semiconductor region of a semiconductor layer;

a plurality of memory cells arranged on the first diffusion region in a matrix shape along first and second directions parallel to a surface of the semiconductor layer, each memory cell including a first transistor and a first memory element;

a second diffusion region in a second semiconductor region of the semiconductor layer, the second semiconductor region being adjacent to one end side in the second direction of the first semiconductor region;

a plurality of second transistors provided on the second diffusion region;

at least one third transistor provided on the other end side in the second direction of the first diffusion region;

a plurality of bit lines provided above the semiconductor layer and extending in the second direction;

a plurality of word lines provided on the first diffusion region and extending in the first direction; and

a source line provided in the first diffusion region,

wherein;

the plurality of second transistors are arranged along a third direction parallel to the surface of the semiconductor layer,

the third direction extends between the first and second directions on a same plane and intersects the first and second directions,

one of the plurality of bit lines is connected to one end of memory cells arranged along the second direction among the plurality of memory cells,

the plurality of bit lines are connected to one end of the plurality of second transistors in a one-to-one correspondence,

one of the plurality of word lines is connected to a gate of the first transistor in memory cells arranged along the first direction among the plurality of memory cells,

the source line is connected to the other end of the plurality of memory cells, and

one end of a conductive path of the third transistor is connected to the plurality of memory cells via the source line.

10. The memory of claim 9, wherein:

the second diffusion region extends in the third direction, and

a longitudinal direction of the second diffusion region is along the third direction.

11. The memory of claim 9, further comprising:

a plurality of first interconnects provided on the second diffusion region and arranged in the first direction, the plurality of first interconnects extending in the second direction,

wherein the plurality of first interconnects are connected to gates of the plurality of second transistors in a one-to-one correspondence.

12. The memory of claim 9, wherein:

the plurality of memory cells include;

a first memory cell; and

a second memory cell adjacent to the first memory cell in the first direction, and

the first diffusion region includes;

a first region above which the first memory cell is provided;

a second region above which the second memory cell is provided; and

a third region that connects the first region and the second region.

13. The memory of claim 9, wherein:

the first transistor includes a first semiconductor portion extending in a fourth direction perpendicular to the surface of the semiconductor layer,

a gate of the first transistor is provided on a first gate insulating film on a side face in the second direction of the first semiconductor portion,

a first terminal of the first transistor is provided on a side of the first diffusion region of the first semiconductor portion,

a second terminal of the first transistor is provided on an opposite side in the fourth direction of the first terminal of the first semiconductor portion,

the memory element is provided above the first semiconductor portion in the fourth direction and is connected to the second terminal,

the second transistor includes a second semiconductor portion extending in the fourth direction,

a gate of the second transistor is provided on a second gate insulating film on a side face in the second direction of the second semiconductor portion,

a third terminal of the second transistor is provided on the side of the second diffusion region of the second semiconductor portion,

a fourth terminal of the second transistor is provided on the opposite side of the third terminal of the second semiconductor portion in the fourth direction, and

the fourth terminal is connected to the bit line.

14. The memory of claim 9, wherein:

the first transistor includes a first semiconductor portion extending in a fourth direction perpendicular to the surface of the semiconductor layer,

the second transistor includes a plurality of second semiconductor portions each extending in the fourth direction, and

each of the plurality of second semiconductor portions has a same size as the first semiconductor portion.

15. The memory of claim 9, wherein:

the first transistor includes a first semiconductor portion extending in a fourth direction perpendicular to the surface of the semiconductor layer,

the second transistor includes a second semiconductor portion extending in the fourth direction, and

a first dimension in the second direction of the second semiconductor portion is larger than a second dimension in the second direction of the first semiconductor portion.

16. The memory of claim 9, wherein an insulating film is provided between the first diffusion region and the second diffusion region.

17. A variable resistance memory comprising:

a first diffusion region in a first semiconductor region of a semiconductor layer;

a plurality of memory cells arranged on the first diffusion region in a matrix shape along first and second directions parallel to a surface of the semiconductor layer, each memory cell including a first transistor and a first memory element;

a second diffusion region in a second semiconductor region of the semiconductor layer, the second semiconductor region being adjacent to one end side in the second direction of the first semiconductor region; and

a plurality of second transistors provided on the second diffusion region,

wherein;

the plurality of second transistors are arranged along a third direction parallel to the surface of the semiconductor layer, and

the third direction extends between the first and second directions on a same plane and intersects the first and second directions,

the first transistor includes a first semiconductor portion extending in a fourth direction perpendicular to the surface of the semiconductor layer,

a gate of the first transistor is provided on a first gate insulating film on a side face in the second direction of the first semiconductor portion,

a first terminal of the first transistor is provided on a side of the first diffusion region of the first semiconductor portion,

a second terminal of the first transistor is provided on an opposite side in the fourth direction of the first terminal of the first semiconductor portion,

the memory element is provided above the first semiconductor portion in the fourth direction and is connected to the second terminal,

the second transistor includes a second semiconductor portion extending in the fourth direction,

a gate of the second transistor is provided on a second gate insulating film on a side face in the second direction of the second semiconductor portion,

a third terminal of the second transistor is provided on the side of the second diffusion region of the second semiconductor portion,

a fourth terminal of the second transistor is provided on the opposite side of the third terminal of the second semiconductor portion in the fourth direction, and

the fourth terminal is connected to the bit line.