Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

• US 9,905,643 B1
• Filed: 08/26/2016
• Issued: 02/27/2018
• Est. Priority Date: 08/26/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Miller, Eric R., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/248,237
• Publication Number:
  US 20180061945A1
• Time in Patent Office: 550 Days
• Field of Search: 438157, 438282, 438283, 438284, 438300, 438304, 438686, 257213, 257344, 257347, 257365, 257401, 257E21409, 257E21415, 257E21421, 257E21431, 257E29004, 257E29022, 257E29117, 257E29128, 257E29137, 257E29286, 257E29296
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H05K 999/99 : dummy group

Abstract

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

Claims

1. A semiconductor structure comprising at least:

a substrate;

at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;

a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;

a source region;

a drain region;

a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; and

a second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the drain region.

2. The semiconductor structure of claim 1, wherein a thickness of each semiconductor layer in the alternating stack is between 3 nm and 60 nm.

3. The semiconductor structure of claim 1, wherein the alternating stack is disposed in contact with the substrate.

4. The semiconductor structure of claim 1, further comprising:

a first dielectric layer formed on and in contact with a top surface of the source region; and

a second dielectric layer formed on and in contact with a top surface of the drain region.

5. The semiconductor structure of claim 4, further comprising:

a first spacer disposed between and in contact with the metal gate and the first dielectric layer, the first spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the first plurality of epitaxially grown interconnects; and

a second spacer disposed between and in contact with the metal gate and the second dielectric layer, the second spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the second plurality of epitaxially grown interconnects.

6. The semiconductor structure of claim 1, wherein the epitaxially grown interconnect material contacts sidewall portions of the source region between the first plurality of epitaxially grown interconnects.

7. The semiconductor structure of claim 6, wherein the epitaxially grown interconnect material contacts sidewall portions of the drain region between the first plurality of epitaxially grown interconnects.

8. The semiconductor structure of claim 1, further comprising a cap layer in contact with the metal gate.

9. The semiconductor structure of claim 1, wherein each epitaxially grown interconnect of the first plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith, and wherein each epitaxially grown interconnect of the second plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith.

10. An integrated circuit comprising:

a semiconductor structure comprising at least;

a substrate;

at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;

a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;

a source region;

a drain region;

a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; and

a second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the drain region.

11. The integrated circuit of claim 10, wherein a thickness of each semiconductor layer in the alternating stack is between 3 nm and 60 nm.

12. The integrated circuit of claim 10, wherein the alternating stack is disposed in contact with the substrate.

13. The integrated circuit of claim 10, wherein the semiconductor structure further comprises:

a first dielectric layer formed on and in contact with a top surface of the source region; and

a second dielectric layer formed on and in contact with a top surface of the drain region.

14. The integrated circuit of claim 13, wherein the semiconductor structure further comprises:

a first spacer disposed between and in contact with the metal gate and the first dielectric layer, the first spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the first plurality of epitaxially grown interconnects; and

a second spacer disposed between and in contact with the metal gate and the second dielectric layer, the second spacer layer being further disposed on and in contact with a top-most epitaxially grown interconnect in the second plurality of epitaxially grown interconnects.

15. The integrated circuit of claim 10, wherein the epitaxially grown interconnect material contacts sidewall portions of the source region between the first plurality of epitaxially grown interconnects.

16. The integrated circuit of claim 15, wherein the epitaxially grown interconnect material contacts sidewall portions of the drain region between the first plurality of epitaxially grown interconnects.

17. The integrated circuit of claim 10, wherein the semiconductor structure further comprises a cap layer in contact with the metal gate.

18. The integrated circuit of claim 10, wherein each epitaxially grown interconnect of the first plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith, and wherein each epitaxially grown interconnect of the second plurality of epitaxially grown interconnects extends above and below the one semiconductor layer in contact therewith.