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Silicon on insulator device with partially recessed gate

  • US 9,905,648 B2
  • Filed: 02/07/2014
  • Issued: 02/27/2018
  • Est. Priority Date: 02/07/2014
  • Status: Active Grant
First Claim
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1. A transistor, comprising:

  • a raised doped source region that extends above a top surface of an active region of a substrate and downward to a buried oxide layer;

    a raised doped drain region that extends above the top surface of the active region of the substrate and downward to the buried oxide layer; and

    a gate stack partially recessed to a recess depth below the top surface of the active region of the substrate, the gate stack including;

    an epitaxial channel extending between the raised doped source and drain regions;

    a high-k gate dielectric in contact with the epitaxial channel, the gate dielectric having a dielectric length;

    a metal gate having a gate length that exceeds the dielectric length by a distance that defines an undercut region; and

    a single, continuous encapsulant in contact with a top surface, sidewalls, and an underside of the metal gate, the single, continuous encapsulant filling the undercut region.

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