Silicon on insulator device with partially recessed gate
First Claim
1. A transistor, comprising:
- a raised doped source region that extends above a top surface of an active region of a substrate and downward to a buried oxide layer;
a raised doped drain region that extends above the top surface of the active region of the substrate and downward to the buried oxide layer; and
a gate stack partially recessed to a recess depth below the top surface of the active region of the substrate, the gate stack including;
an epitaxial channel extending between the raised doped source and drain regions;
a high-k gate dielectric in contact with the epitaxial channel, the gate dielectric having a dielectric length;
a metal gate having a gate length that exceeds the dielectric length by a distance that defines an undercut region; and
a single, continuous encapsulant in contact with a top surface, sidewalls, and an underside of the metal gate, the single, continuous encapsulant filling the undercut region.
2 Assignments
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Accused Products
Abstract
Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.
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Citations
20 Claims
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1. A transistor, comprising:
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a raised doped source region that extends above a top surface of an active region of a substrate and downward to a buried oxide layer; a raised doped drain region that extends above the top surface of the active region of the substrate and downward to the buried oxide layer; and a gate stack partially recessed to a recess depth below the top surface of the active region of the substrate, the gate stack including; an epitaxial channel extending between the raised doped source and drain regions; a high-k gate dielectric in contact with the epitaxial channel, the gate dielectric having a dielectric length; a metal gate having a gate length that exceeds the dielectric length by a distance that defines an undercut region; and a single, continuous encapsulant in contact with a top surface, sidewalls, and an underside of the metal gate, the single, continuous encapsulant filling the undercut region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of making a transistor, the method comprising:
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doping an active area of a silicon substrate having a buried oxide layer therein, to form doped source and drain regions; forming a planar epitaxial channel extending between the source and drain regions, the planar epitaxial channel being at least partially recessed below an upper surface of an active region of the substrate; forming a high-k gate dielectric in contact with the planar epitaxial channel, the gate dielectric having a dielectric length; forming a metal gate over the high-k gate dielectric, the metal gate surrounded on three sides by a metal barrier seed layer, the metal gate having a gate length that exceeds the dielectric length by a distance that defines an undercut region; encapsulating the metal gate with a single, continuous encapsulant in contact with a top surface, sidewalls, and an underside of the metal gate, the single, continuous encapsulant filling the undercut region; raising the doped source and drain regions by forming additional doped epitaxial layers in contact with the source and drain regions; covering the transistor with an insulator; and forming metal contacts to the metal gate and the source and drain regions. - View Dependent Claims (13, 14, 15, 16, 17, 20)
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18. A transistor, comprising:
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a semiconductor substrate having a buried insulating layer therein; a drain region that extends downward to the buried insulating layer; a source region that extends downward to the buried insulating layer, wherein the source region and drain region extend above a top surface of the substrate; an epitaxial channel extending between the source and drain regions; a gate stack partially recessed to a recess depth below the top surface of the substrate, the gate stack including; a gate dielectric in contact with the epitaxial channel, the gate dielectric having a dielectric length; and a metal gate having a gate length that exceeds the dielectric length by a distance that defines an undercut region; and a single, continuous encapsulant in contact with a top surface, sidewalls, and an underside of the metal gate, the encapsulant being positioned in the undercut region. - View Dependent Claims (19)
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Specification