Fabrication of a vertical fin field effect transistor with a reduced contact resistance

• US 9,905,663 B2
• Filed: 06/24/2016
• Issued: 02/27/2018
• Est. Priority Date: 06/24/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US15/191,566
• Publication Number:
  US 20170373159A1
• Time in Patent Office: 613 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Claims

1. A method of forming a vertical fin field effect transistor (vertical fmFET) with a reduced source/drain contact resistance, comprising:

forming one or more doped regions in a substrate;

forming a plurality of vertical fins on at least one of the one or more doped regions;

heat treating the one or more doped regions in the substrate and the plurality of vertical fins on the at least one of the one or more doped regions to diffuse dopant from the doped region in contact with the plurality of vertical fins into a lower portion of each of the plurality of vertical fins;

removing an upper portion of at least one of the plurality of vertical fins, wherein the lower portion of the at least one of the plurality of vertical fins remains as an extension on the at least one of the one or more doped regions; and

forming a bottom source/drain contact on the extension and the at least one of the one or more doped regions.

2. The method of claim 1, wherein the heat treating is at a temperature in the range of about 800°

C. to about 1200°

C.

3. The method of claim 1, wherein the extension has a height in the range of about 10 nm to about 40 nm measured from an upper surface of the doped region.

4. The method of claim 1, wherein the extension is electrically coupled with the at least one of the one or more doped regions, and increases the interfacial surface area between the bottom source/drain contact and the at least one of the one or more doped region.

5. The method of claim 1, wherein the dopant concentration in the one or more doped regions is in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to about 2×

10²¹ cm<sup>−

3</sup>.

6. The method of claim 1, wherein the plurality of vertical fins are made of a material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), III-V compound semiconductor materials, and II-VI compound semiconductor materials.

7. The method of claim 1, further comprising forming a gate structure on at least one of the plurality of vertical fins on the at least one of the one or more doped regions, and leaving at least one of the plurality of vertical fins on the at least one of the one or more doped regions without a gate structure.

8. The method of claim 7, further comprising forming an interlayer dielectric on the at least one of the one or more vertical fins with the gate structure and the at least one of the one or more vertical fins without the gate structure;

and

removing a portion of the interlayer dielectric on the at least one of the one or more vertical fins without the gate structure to expose the vertical fin(s) without the gate structure.