Gate and field electrode trench formation process

• US 9,905,675 B1
• Filed: 12/22/2016
• Issued: 02/27/2018
• Est. Priority Date: 12/22/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Ma, Ling
• Primary Examiner(s): Shook, Daniel
• Application Number:
  US15/387,739
• Time in Patent Office: 432 Days
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An upper portion of a field electrode trench and a gate trench are simultaneously formed in the main surface of a substrate to approximately the same depth. A first protective layer is formed that completely fills the gate trench and lines the upper field electrode trench. The first protective layer is removed from the bottom of the upper trench and semiconductor material is removed thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer. An electrically conductive field electrode and a field electrode dielectric are formed in the field electrode trench. At least some of the first protective layer is removed from the gate trench. A conformal gate dielectric layer is formed on the substrate. An electrically conductive gate electrode is formed in the gate trench while the field electrode remains covered by the gate dielectric layer.

Claims

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate comprising a main surface;

simultaneously forming an upper portion of a field electrode trench and a gate trench in the main surface of the substrate to approximately the same depth;

forming a first protective layer on the substrate, the first protective layer completely filling the gate trench and lining sidewalls of the upper portion of the field electrode trench, a bottom of the upper portion of the field electrode trench being exposed from the first protective layer;

removing semiconductor material from the exposed bottom of the upper portion of the field electrode trench thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer;

forming an electrically conductive field electrode and a field electrode dielectric in the upper and lower portions of the field electrode trench while the gate trench remains completely filled by the first protective layer;

removing at least some of the first protective layer from the gate trench;

forming a conformal gate dielectric layer that covers the field electrode and lines sidewalls of the gate trench after removing the at least some of the first protective layer; and

forming an electrically conductive gate electrode in the gate trench while the field electrode remains covered by the gate dielectric layer.

2. The method of claim 1, wherein simultaneously forming an upper portion of a field electrode trench and the gate trench comprises:

forming a first mask on the substrate, the first mask comprising first and second openings; and

etching semiconductor material away simultaneously from sections of the substrate that are exposed by the first and second openings.

3. The method of claim 1, wherein forming the first protective layer comprises:

forming a conformal first dielectric layer that lines the bottom and sidewalls of the upper portion of the field electrode trench and completely fills the gate trench; and

etching a section of the first dielectric layer that lines the bottom of the upper portion of the field electrode trench.

4. The method of claim 3, wherein after etching the section of the first dielectric layer, the upper portion of the field electrode trench is wider than the lower portion of the field electrode trench, and the first protective layer remains on the sidewalls of the upper portion of the field electrode trench.

5. The method of claim 4, wherein forming the field electrode and the field electrode dielectric comprises:

depositing a conformal field electrode dielectric layer on the substrate, the conformal field electrode dielectric layer covering the first protective layer in the upper portion and lining the sidewalls of the field electrode trench in the lower portion; and

depositing a conformal electrically conductive field electrode layer on the substrate after depositing the field electrode dielectric layer such that a center of the field electrode trench is completely filled by the field electrode layer.

6. The method of claim 5, further comprising removing sections of the field electrode dielectric layer and the field electrode layer that are disposed outside of the field electrode trench thereby exposing the main surface.

7. The method of claim 4, further comprising, after forming the conformal gate dielectric layer:

forming oppositely doped source and body regions in the substrate, the source region extending to the main surface and laterally extending between the field electrode trench and the gate trench, the body region being disposed beneath the source region and laterally extending between the field electrode trench and the gate trench.

8. The method of claim 7, further comprising, after forming the source and body regions:

depositing an interlayer dielectric layer on the main surface, the interlayer dielectric layer covering the field electrode and the gate electrode.

9. The method of claim 8, further comprising:

forming an opening in the interlayer dielectric layer over the field electrode trench, the opening exposing a top of the field electrode.

10. The method of claim 9, wherein forming the opening in the interlayer dielectric layer comprises removing a complete section of the interlayer dielectric layer that is disposed over the field electrode trench and completely removing the first protective layer from the upper portion of the field electrode trench.

11. The method of claim 10, further comprising, after forming the opening in the interlayer dielectric layer:

introducing dopants into the opening thereby forming a body extension region that extends from the sidewalls of the upper portion of the field electrode trench into the substrate, the body extension region having the same conductivity type as the body region and connecting to the body region.

12. The method of claim 1, wherein removing at least some of the first protective layer from the gate trench comprises, after forming the electrically conductive field electrode and the field electrode dielectric:

forming a second mask on the main surface, the second mask covering the field electrode and the field electrode dielectric and comprising an opening that exposes the gate trench; and

etching the first protective layer away from the gate trench.

13. The method of claim 12, wherein the first protective layer is partially etched away from the gate trench such that a portion of the first protective layer remains at the bottom of the gate trench.

14. The method of claim 1, wherein the field electrode trench is formed to be to be wider than the gate trench, and wherein the gate trench is formed to be longer than the field electrode trench.

15. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate comprising a main surface;

forming a field electrode trench comprising a dielectrically insulated field electrode and a gate trench comprising a dielectrically insulated gate electrode in the substrate, the field electrode trench being wider and deeper than the gate trench, the gate trench being longer than the field electrode trench, wherein forming the field electrode trench comprising the dielectrically insulated field electrode and the gate trench comprising a dielectrically insulated gate electrode comprises;

forming an upper portion of the field electrode trench and the gate trench simultaneously;

forming a first protective layer that completely fills the gate trench;

removing semiconductor material from a bottom of the upper portion of the field electrode trench thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer;

forming an electrically conductive field electrode and a field electrode dielectric in the upper and lower portions of the field electrode trench while the gate trench remains completely filled by the first protective layer;

removing at least some of the first protective layer from the gate trench;

covering the field electrode with a second protective layer; and

forming an electrically conductive gate electrode and a gate trench dielectric in the gate trench while the field electrode remains covered by the second protective layer.

16. The method of claim 15, wherein forming the upper portion of the field electrode trench and the gate trench simultaneously comprises:

forming a first mask on the substrate, the first mask comprising first and second openings; and

etching semiconductor material away simultaneously from sections of the substrate that are exposed by the first and second openings.

17. The method of claim 15, further comprising, after covering the field electrode with the second protective layer:

forming oppositely doped source and body regions in the substrate, the source region extending to the main surface and laterally extending between the field electrode trench and the gate trench, the body region being disposed beneath the source region and laterally extending between the field electrode trench and the gate trench.

18. The method of claim 17, further comprising, after forming the source and body regions:

depositing an interlayer dielectric layer on the main surface, the interlayer dielectric layer covering the field electrode and the gate electrode.

19. The method of claim 18, further comprising:

removing a removing a complete section of the interlayer dielectric layer that is disposed over the field electrode trench and removing all dielectric material from the upper portion of the field electrode trench thereby forming an opening that exposes a top of the field electrode; and

introducing dopants into the opening thereby forming a body extension region that extends from the sidewalls of the upper portion of the field electrode trench into the substrate, the body extension region having the same conductivity type as the body region and connecting to the body region.

20. The method of claim 19, further comprising removing portions of the source regions that are exposed by the opening.