Active device structure with oxide channel layer having degree of crystallinity and method thereof

• US 9,905,701 B2
• Filed: 03/16/2016
• Issued: 02/27/2018
• Est. Priority Date: 04/13/2015
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Yeh, Po-Liang, Wu, Chen-Chung, Chang, Chun-An, You, Jiang-Jin, Chang, Chia-Ming
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US15/072,301
• Publication Number:
  US 20160300951A1
• Time in Patent Office: 713 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An active device structure and a method of fabricating an active device are provided. The active device structure includes a gate, an oxide channel layer, a source, a drain and a high power deposited insulation layer. The gate and the oxide channel layer are overlapped in a top and bottom manner. The oxide channel layer includes a top layer and a bottom layer having a crystalline structure different from a crystalline structure of the top layer. The source and the drain both contact the oxide channel layer, wherein a gap separating the source and the drain defines a channel area. The high power deposited insulation layer contacts the top layer of the oxide channel layer. The top layer of the oxide channel layer provides the effect of blocking light, which solves the problem of threshold voltage shift due to the light irradiation on the oxide channel layer.

Claims

1. An active device structure, comprising:

a gate;

an oxide channel layer, located over or under the gate, wherein the oxide channel layer comprises a top layer and a bottom layer having a crystalline structure different from a crystalline structure of the top layer, wherein the crystalline structure of the top layer is a body-centered cubic (BBC) or a face-centered cubic (FCC), and a degree of crystallinity of the top layer is higher than a degree of crystallinity of the bottom layer;

a source, contacting the oxide channel layer;

a drain, contacting the oxide channel layer, wherein a gap separating the source and the drain defines a channel area on the oxide channel layer; and

an insulation layer, contacting the top layer of the oxide channel layer.

2. The active device structure as recited in claim 1, wherein a material of the insulation layer comprises silicon oxide.

3. The active device structure as recited in claim 1, wherein a ratio of a thickness of the top layer to a thickness of the bottom layer is from 1:

5 to 1;

9.

4. The active device structure as recited in claim 1, wherein the bottom layer has an amorphous crystalline structure.

5. The active device structure as recited in claim 1, wherein an oxygen content of the top layer is lower than an oxygen content of the bottom layer.

6. The active device structure as recited in claim 1, further comprising a gate insulating layer, wherein the gate insulating layer is located between the gate and the oxide channel layer, and the oxide channel layer, the source, and the drain are located between the insulation layer and the gate insulating layer.

7. The active device structure as recited in claim 1, further comprising a protective layer, wherein the insulation layer is located between the gate and the oxide channel layer, and the protective layer covers the gate and the insulation layer.

8. The active device structure as recited in claim 1, wherein a material of the top layer and the bottom layer of the oxide channel layer comprises indium gallium zinc oxide.

9. The active device structure as recited in claim 1, wherein a surface area of the top layer of the oxide channel layer is approximately equal to a contact area of the oxide channel layer in contact with the insulation layer.

18. The active device structure as recited in claim 1, wherein the insulation layer is formed by a high power depositing step, and a value of energy density of the high power depositing step is from 0.14 W/cm² to 0.37 W/cm².

10. A method of fabricating an active device structure, comprising:

forming a gate, an oxide channel layer, a source, and a drain, wherein the gate and the oxide channel layer are overlapped in a top and bottom manner, the source and the drain both contact the oxide channel layer, and a gap separating the source and the drain defines a channel area on the oxide channel layer;

performing a high power depositing step to form an insulation layer contacting the oxide channel layer, wherein a value of energy density of the high power depositing step is from 0.14 W/cm² to 0.37 W/cm²; and

performing an annealing step, such that the oxide channel layer comprises a bottom layer and a top layer contacting with the insulation layer, and a crystalline structure of the top layer is different from a crystalline structure of the bottom layer, wherein the crystalline structure of the top layer is a body-centered cubic (BBC) or a face-centered cubic (FCC), and a degree of crystallinity of the top layer is higher than a degree of crystallinity of the bottom layer, wherein a processing temperature of the annealing step is from 200°

C. to 300°

C.

11. The method for fabricating the active device structure as recited in claim 10, wherein a value of energy density of the high power depositing step is from 0.21 W/cm² to 0.28 W/cm².

12. The method for fabricating the active device structure as recited in claim 10, wherein the annealing step is performed under atmospheric environment.

13. The method for fabricating the active device structure as recited claim 10, wherein the processing temperature of the annealing step is 230°

C., and a processing duration of the annealing step is 120 minutes.

14. The method for fabricating the active device structure as recited claim 10, wherein the annealing steps is performed after the high power depositing step.

15. The method for fabricating the active device structure as recited claim 10, wherein the insulation layer is formed between the gate and the oxide channel layer.

16. The method for fabricating the active device structure as recited in claim 10, further comprising forming a gate insulating layer between the gate and the oxide channel layer, and the oxide channel layer, the source, and the drain being located between the insulation layer and the gate insulating layer.

17. The method for fabricating the active device structure as recited in claim 10, wherein a material of the insulation layer is silicon oxide.