Receiver circuit

• US 9,906,064 B2
• Filed: 09/22/2014
• Issued: 02/27/2018
• Est. Priority Date: 09/22/2014
• Status: Expired due to Fees

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Inventors: McFarthing, Anthony Lawrence
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): Inge, Joseph
• Application Number:
  US14/492,413
• Publication Number:
  US 20160087479A1
• Time in Patent Office: 1,254 Days
• Field of Search: 307104
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H02J 50/20 using microwaves or radio frequency waves
• CPC Class Codes: H02J 50/40 using two or more transmitting or receiving devices H02J50/50 takes precedence
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer

Abstract

A receiver circuit and a device incorporating a receiver circuit are described, including a receiver circuit comprising a first rectifier arranged to receive a signal from an antenna, a second rectifier arranged to receive the signal from the antenna, and a first depletion mode NMOS transistor switch connected between the first rectifier and a first output of the receiver circuit, wherein a drain of the first transistor switch is connected to a first output of the first rectifier, a source of the first transistor switch comprises the first output of the receiver circuit, and a gate of the first transistor switch is arranged to receive a voltage based on an output of the second rectifier, such that the transistor switch is opened when a level of the signal from the antenna exceeds a predetermined level.

Claims

1. A receiver circuit comprising:

a first rectifier configured to receive a signal from an antenna;

a second rectifier configured to receive the signal from the antenna;

a first transistor connected between the first rectifier and a first output of the receiver circuit, the first transistor including a drain connected to a first output of the first rectifier, a source connected to the first output of the receiver circuit, and a gate to receive a voltage based on an output of the second rectifier, wherein the first transistor is configured to be in an open state when a level of the signal from the antenna exceeds a predetermined level; and

a second transistor connected between the first rectifier and a second output of the receiver circuit, the second transistor including a drain connected to the second output of the first rectifier, a source connected to the second output of the receiver circuit, and a gate to receive the voltage, wherein the second transistor is configured to be in the open state when the level of the signal from the antenna exceeds the predetermined level.

2. The receiver circuit of claim 1, further comprising a circuit configured to provide the voltage to the gate of the first transistor.

3. The receiver circuit of claim 2, wherein the circuit comprises at least one of a filter and a potential divider coupled between the output of the second rectifier and the gate of the first transistor.

4. The receiver circuit of claim 1, wherein the first rectifier comprises a full-wave rectifier.

5. The receiver circuit of claim 1, wherein the signal is a differential signal comprising a first antenna signal and a second antenna signal, and the first rectifier comprises:

a first diode connected between a first node and the drain of the first transistor; and

a second diode connected between a second node and the drain of the second transistor.

6. The receiver circuit of claim 5, wherein the second rectifier comprises:

a third diode connected between the first node and the output of the second rectifier; and

a fourth diode connected between the second node and the output of the second rectifier.

7. The receiver circuit of claim 1, wherein the gate of the first transistor is coupled to the gate of the second transistor.

8. The receiver circuit of claim 1, wherein the second rectifier comprises a full-wave rectifier.

9. The receiver circuit of claim 1, wherein the first rectifier is configured to provide a substantially positive voltage relative to a ground voltage, and the second rectifier is configured to provide a substantially negative voltage relative to the ground voltage.

10. The receiver circuit of claim 1, wherein the first output of the receiver circuit is coupled to a communications circuit.

11. The receiver circuit of claim 10, wherein the communications circuit is at least one of a near-field communications (NFC) circuit and a radio frequency identification (RFID) circuit.

12. The receiver circuit of claim 1, wherein the voltage is configured to transition the first transistor to the open state when the signal received by the antenna is a wireless charging signal.

13. The receiver circuit of claim 1, wherein the first and second transistors comprise depletion mode NMOS transistors.

14. The receiver circuit of claim 5, wherein the first node is configured to receive the first antenna signal, and the second node is configured to receive the second antenna signal.

15. The receiver circuit of claim 6, wherein the first node is connected to an anode of the first diode and to a cathode of the third diode, and the second node is connected to the anode of the second diode and to the cathode of the fourth diode.

16. A device, comprising:

an antenna;

a communications circuit; and

a receiver circuit comprising;

a first rectifier configured to receive a signal from an antenna;

a second rectifier configured to receive the signal from the antenna;

a first transistor connected between the first rectifier and a first output of the receiver circuit, the first transistor including a drain connected to a first output of the first rectifier, a source connected to the first output of the receiver circuit, and a gate to receive a voltage based on an output of the second rectifier, wherein the first transistor is configured to be in an open state when a level of the signal from the antenna exceeds a predetermined level; and

a second transistor connected between the first rectifier and a second output of the receiver circuit, the second transistor including a drain connected to the second output of the first rectifier, a source connected to the second output of the receiver circuit, and a gate to receive the voltage, wherein the second transistor is configured to be in the open state when the level of the signal from the antenna exceeds the predetermined level.

17. The device of claim 16, wherein the communications circuit is at least one of a near-field communications (NFC) circuit and a radio frequency identification (RFID) circuit.

18. The device of claim 16, wherein the voltage is configured to transition the first transistor to the open state when the signal received by the antenna is a wireless charging signal.

19. The receiver circuit of claim 16, wherein the first and second transistors comprise depletion mode NMOS transistors.