Lock detector for phase lock loop

• US 9,906,358 B1
• Filed: 08/31/2016
• Issued: 02/27/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Tayong, Helen
• Application Number:
  US15/253,486
• Publication Number:
  US 20180062827A1
• Time in Patent Office: 545 Days
• Field of Search: 375355
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

Claims

1. An apparatus comprising:

a voltage-controlled oscillator (VCO) configured to provide a plurality of phases of a local clock signal;

a phase comparator configured to receive a phase of the local clock signal and a reference clock signal, and configured to detect a phase error between the phase of the local clock signal and the reference clock and to responsively output a phase-error signal;

a frequency-lock assist (FLA) circuit configured to receive two or more phases of the local clock signal and the reference clock signal, and configured to generate an FLA signal by detecting a number of phases of the two or more phases of the local clock signal having transitions of latched values, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal; and

an error accumulator circuit configured to receive the phase-error signal and the FLA signal, and to responsively provide to the VCO a VCO control signal to lock the local clock signal to the reference clock signal.

2. The apparatus of claim 1, wherein the error accumulator circuit is a loop filter.

3. The apparatus of claim 2, wherein the phase-error signal is received at a second-order input of the loop filter and wherein the FLA signal is received at a first-order input of the loop filter.

4. The apparatus of claim 3, wherein the loop filter is a resistor-capacitor (RC) filter, and wherein the second-order input is at a resistive input of the RC filter and the first-order input is at a capacitive input of the RC filter.

5. The apparatus of claim 1, wherein the FLA signal is configured to set the VCO in a frequency-lock condition, and subsequently the phase-error signal sets the VCO in a frequency and phase-locked condition.

6. The apparatus of claim 1, wherein the VCO comprises a delay-control transistor, and wherein the VCO control signal sets an operating voltage for the delay-control transistor.

7. The apparatus of claim 6, wherein the delay-control transistor adjusts delay characteristics of delay elements in the VCO.

8. The apparatus of claim 7, wherein the delay-control transistor is configured to adjust an RC time-constant of at least one delay element.

9. The apparatus of claim 7, wherein the delay-control transistor is configured to adjust a current through the delay elements in the VCO.

10. The apparatus of claim 1, wherein the FLA circuit comprises:

a plurality of FLA sub-circuits, each FLA sub-circuit configured to receive (i) a respective phase of the plurality of phases of the local clock signal and (ii) the reference clock signal, and to output a partial FLA signal; and

each partial FLA signal provided as an analog signal to a summation node, the partial FLA signals responsively summed to generate the FLA signal.

11. The apparatus of claim 10, wherein each FLA sub-circuit is a first order sub-circuit, each sub-circuit comprising:

a first and a second D Flip-Flop arranged in a shift register configuration, the first and second D Flip-Flops configured to generate the latched values of the respective phase of the local clock signal according to adjacent edges of the reference clock signal; and

an XOR connected to the output of each D Flip-Flop, the XOR configured to receive the latched values, to responsively compare the latched values to determine if a transition occurred, and to responsively generate the partial FLA signal.

12. The apparatus of claim 10, wherein each FLA sub-circuit is a second order circuit, each sub-circuit comprising:

three D Flip-Flops arranged in a shift register configuration, a first and third D Flip-Flop configured to generate the latched values of the respective phase of the local clock signal according to edges of the reference clock signal that are separated by a unit interval; and

an XOR connected to the first and the third D Flip-Flop, the XOR configured to receive the latched values, to responsively compare the latched values to determine if a transition occurred, and to responsively generate the partial FLA signal.

13. The apparatus of claim 10, wherein the FLA circuit comprises 8 FLA sub-circuits, and the FLA signal has a range of values from −

8 to +8.

14. A method comprising:

generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal;

receiving a phase of the local clock signal and a reference clock signal at a phase comparator and responsively generating and outputting a phase-error signal;

generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal generated by detecting a number of phases of the two or more phases of the local signal having transitions of latched values, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal; and

generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

15. The method of claim 14, wherein the error accumulator circuit is a loop filter.

16. The method of claim 15, further comprising receiving the phase-error signal at a second-order input of the loop filter and receiving the FLA signal at a first-order input of the loop filter.

17. The method of claim 16, wherein the loop filter is a resistor-capacitor (RC) filter, and wherein the second-order input is at a resistive input of the RC filter and the first-order input is at a capacitive input of the RC filter.

18. The method of claim 14, wherein the FLA signal sets the VCO in a frequency-lock condition, and subsequently the phase-error signal sets the VCO in a frequency and phase-locked condition.

19. The method of claim 14, wherein the VCO control signal sets an operating voltage for a delay-control transistor in the VCO.

20. The method of claim 19, further comprising adjusting the delay-control transistor to delay characteristics of delay elements in the VCO.

21. The method of claim 20, further comprising adjusting an RC time-constant of at least one delay element in the VCO.

22. The method of claim 20, further comprising adjusting current through at least one delay element in the VCO.

23. The method of claim 14, further comprising:

receiving, at a FLA sub-circuit of a plurality of FLA sub-circuits, a respective phase of the plurality of phases of the local clock signal and the reference clock signal, and responsively forming a partial FLA signal; and

receiving each partial FLA signal as an analog signal at a summation node and responsively generating the FLA signal by summing the received partial FLA signals from each FLA sub-circuit.

24. The method of claim 23, wherein each FLA sub-circuit is a first order sub-circuit, and generating each partial FLA circuit comprises:

latching values of the respective phase of the local clock signal according to adjacent edges of the reference clock signal; and

generating the partial FLA signal by comparing the latched values to detect if a transition of the latched values occurred.

25. The method of claim 23, wherein each FLA sub-circuit is a second order circuit, and generating each partial FLA circuit comprises:

latching values of the respective phase of the local clock signal according to edges of the reference clock signal that are separated by a unit interval; and

generating the partial FLA signal by comparing the latched values to detect if a transition of the latched values occurred.

26. The method of claim 23, wherein the FLA circuit comprises 8 FLA sub-circuits, and the FLA signal has a range of values from −

8 to +8.