Image sensor with tolerance optimizing interconnects

• US 9,907,459 B2
• Filed: 10/05/2015
• Issued: 03/06/2018
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Original Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Inventors: Blanquart, Laurent
• Primary Examiner(s): LUU, THANH X
• Application Number:
  US14/875,591
• Publication Number:
  US 20160155765A1
• Time in Patent Office: 883 Days
• CPC Class Codes: A61B 1/00009 of image signals during a use of endoscope
• CPC Class Codes: A61B 1/051 Details of CCD assembly
• CPC Class Codes: A61B 1/0676 at distal tip of an endoscope
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 31/028 : including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0296 : including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
• CPC Class Codes: H01L 31/0304 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H04N 23/555 : for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
• CPC Class Codes: H04N 23/56 : provided with illuminating means
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 : Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/772 : comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 : comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/78 : Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Claims

1. An imaging sensor comprising:

a plurality of substrates comprising a first substrate and at least one second, subsequent supporting substrate;

a pixel array;

a plurality of interconnects; and

a plurality of supporting circuits;

wherein the first substrate of the plurality of substrates comprises a plurality of pixel read buses and the pixel array, wherein the pixel array comprises a plurality of pixel groups, and wherein there is one pixel read bus per pixel group;

wherein the at least one second, subsequent supporting substrate comprises a plurality of circuit buses and the plurality of supporting circuits, including a plurality of readout supporting circuits, with one circuit bus per readout supporting circuit;

wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array via the plurality of interconnects disposed between said first substrate and said at least one second, subsequent supporting substrate;

wherein each of the plurality of interconnects reads out a pixel group to one of the circuit buses;

wherein said at least one second, subsequent supporting substrate is disposed behind said first substrate relative to an object to be imaged;

wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array.

2. The imaging sensor of claim 1, wherein said imaging sensor is backside illuminated.

3. The imaging sensor of claim 1, wherein the plurality of substrates further comprise a plurality of second, subsequent supporting substrates.

4. The imaging sensor of claim 3, wherein said first substrate and said plurality of second, subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.

5. The imaging sensor of claim 1, wherein said pixel array covers a substantial majority of a surface of said first substrate.

6. The imaging sensor of claim 1, wherein one of said supporting circuits is an analog to digital converter.

7. The imaging sensor of claim 1, wherein one of said supporting circuits is an amplifier circuit.

8. The imaging sensor of claim 1, wherein said at least one second, subsequent supporting substrate is aligned in the Z-dimension with said first substrate in a stacked configuration.

9. The imaging sensor of claim 1, wherein said second, subsequent supporting substrate is disposed behind said first substrate and displaced laterally therefrom.

10. The imaging sensor of claim 1, wherein each of the plurality of interconnects is a bump and comprises a bump to bump distance that is greater than two pixels in width.

11. The imaging sensor of claim 10, wherein the bump to bump distance is greater than four pixels in width.

12. The imaging sensor of claim 10, wherein the bump to bump distance is greater than eight pixels in width.

13. The imaging sensor of claim 10, wherein the bump pitch is greater than √

{square root over ((N*PixelPitch_x)²+(M*PixelPitch_y)²)}.

14. The imaging sensor of claim 1, wherein the pixel array is comprised of a plurality of pixel columns, wherein each pixel column comprises a plurality of pixels;

wherein each of the plurality of pixel columns within the pixel array is read to a bus, starting from a first column that is read from a common origin, wherein a second column is read from a first row that is different from the pixel column that was previously read with respect to the second column and different from the pixel column that is read subsequent with respect to the second column.

15. The imaging sensor of claim 14, wherein said first row is spaced at least two row positions away from the row position of the previously read pixel column and the subsequently read pixel column.

16. The imaging sensor of claim 1, wherein the readout supporting circuits and the corresponding pixel groups have different aspect ratios.

17. The imaging sensor of claim 1, wherein each of the pixel groups is a column of pixels.

18. The imaging sensor of claim 17, wherein a column of pixels is 1 pixel wide from a top row to a bottom row;

or wherein a column of pixels is 2 pixels wide from a top row to a bottom row;

or wherein a column of pixels is 3 pixels wide from a top row to a bottom row;

or wherein a column of pixels is 4 pixels wide from a top row to a bottom row.

19. The imaging sensor of claim 17, wherein a column of pixels is less than the entire column from a top row to a bottom row that is 1 pixel wide;

or wherein a column of pixels is less than the entire column from a top row to a bottom row that is 2 pixels wide;

or wherein a column of pixels is less than the entire column from a top row to a bottom row that is 3 pixels wide;

or wherein a column of pixels is less than the entire column from a top row to a bottom row that is 4 pixels wide.

20. The imaging sensor of claim 1, wherein one pixel read bus reads out one pixel group to one circuit bus of the readout supporting circuit, wherein the readout supporting circuit has an area that is substantially the same as an area of the pixel group.