Voltage regulator training

• US 9,910,484 B2
• Filed: 11/26/2013
• Issued: 03/06/2018
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Muljono, Harry, Sun, Linda K.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Harrington, Cheri
• Application Number:
  US14/091,125
• Publication Number:
  US 20150149796A1
• Time in Patent Office: 1,561 Days
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.

Claims

1. An apparatus comprising:

an analog front end (AFE) on a processor die;

an on-die voltage regulator coupled with the AFE, the on-die voltage regulator to supply a first voltage to the AFE, wherein the on-die voltage regulator is on the processor die; and

an external voltage regulator external to the processor die coupled with the AFE to supply a second voltage to the AFE,

wherein the on-die voltage regulator is to dynamically alter the first voltage to reduce power consumption of the AFE based at least in part on a result of a training loop performed on system power up or system reset, wherein the training loop is to include detection of whether there is a first margin failure of the AFE based at least in part on an adjustment of the first voltage and the training loop is also to include detection of a second margin failure based at least in part on an adjustment of the second voltage, and wherein the external voltage regulator is to dynamically alter the second voltage to reduce power consumption of the AFE based at least in part on the training loop performed on system power up or system reset.

2. The apparatus of claim 1, wherein the external voltage regulator is further coupled with a double data rate fourth generation (DDR4) dynamic random access memory (DRAM), the external voltage regulator to supply the second voltage to the DRAM.

3. The apparatus of claim 1, wherein the first voltage is a low noise voltage.

4. The apparatus of claim 1, wherein the on-die voltage regulator is further to supply the first voltage to an input/output (I/O) analog circuit coupled with the AFE, wherein the I/O analog circuit is on the processor die.

5. The apparatus of claim 1, wherein the training loop is performed by a basic input/output system (BIOS).

6. The apparatus of claim 1, wherein the apparatus includes a memory controller on the processor die.

7. A method comprising:

setting, by a basic input/output system (BIOS), a voltage output of an on-die voltage regulator to a first voltage;

identifying, by the BIOS, an occurrence of a margin failure at an analog front end (AFE) that is to receive the first voltage; and

adjusting, by the BIOS in response to the occurrence of the margin failure, the voltage output of the on-die voltage regulator by an increment, wherein the on-die voltage regulator is on a processor die and the AFE is on the processor die,

wherein the margin failure is a first margin failure and the increment is a first increment, and further comprising setting, by the BIOS, a voltage output of an external voltage regulator external to the processor die to a second voltage;

identifying, by the BIOS, an occurrence of a second margin failure at a dynamic random access memory (DRAM) that is to receive the second voltage; and

adjusting, by the BIOS and based at least in part on the occurrence of the second margin failure, the voltage output of the external voltage regulator by a second increment.

8. The method of claim 7, wherein the first increment or the second increment are a negative value.

9. The method of claim 7, wherein the first increment or the second increment are a positive value.

10. The method of claim 7, wherein the DRAM is a double data rate fourth generation (DDR4) DRAM.

11. The method of claim 7, wherein the AFE is coupled with an input/output analog circuit that is configured to receive the first voltage from the on-die voltage regulator, wherein the input/output analog circuit is on the processor die.

12. The method of claim 7, wherein the setting the voltage output of the on-die voltage regulator is based at least in part on a power-on event or a reset event.

13. A system comprising:

a memory controller coupled with a dynamic random access memory (DRAM);

an on-die voltage regulator to supply a first voltage to an analog front end (AFE) coupled with the DRAM; and

an external voltage regulator to supply a second voltage to the DRAM,

wherein the on-die voltage regulator and the AFE are on a processor die, the external voltage regulator is external to the processor die, and wherein the on-die voltage regulator is to alter the first voltage based at least in part on a first signal from a basic input/output system (BIOS) and the external voltage regulator is to alter the second voltage based at least in part on a second signal from the BIOS.

14. The system of claim 13, wherein the on-die voltage regulator is further to supply the first voltage to an input/output analog circuit coupled with the AFE, wherein the input/output analog circuit is on the processor die.

15. The system of claim 13, wherein the DRAM is a double data rate fourth generation (DDR4) DRAM.

16. The system of claim 13, wherein the first signal is a first output of a training loop of the BIOS and the second signal is a second output of the training loop of the BIOS.

17. The system of claim 13, wherein the first voltage is a low noise voltage.