Method of managing a memory, and a memory system

• US 9,910,607 B2
• Filed: 07/16/2014
• Issued: 03/06/2018
• Est. Priority Date: 12/23/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Sangyong, Han, Jinman
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/332,892
• Publication Number:
  US 20150178000A1
• Time in Patent Office: 1,329 Days
• Field of Search: 36518509
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 29/024 in decoders

Abstract

In one embodiment, the method includes determining whether a selection transistor of a currently programmed memory string in the memory has deteriorated, and copying data in the currently programmed memory string to a different memory string of the memory if the determining determines the selection transistor has deteriorated.

Claims

1. A method of managing a memory, comprising:

applying a gate voltage to a gate of a selection transistor of a currently programmed memory string in the memory;

determining whether the selection transistor turns off based on output from the currently programmed memory string;

determining whether the selection transistor has deteriorated based on the determining whether the selection transistor turns off; and

copying data in the currently programmed memory string to a different memory string of the memory if the determining determines the selection transistor has deteriorated.

2. The method of claim 1, wherein the gate voltage is a first gate voltage, the copying applies a second gate voltage to the selection transistor, and the first gate voltage is greater than the second gate voltage.

3. The method of claim 1, wherein the gate voltage is greater than applied during a read operation.

4. The method of claim 1, wherein

the currently programmed memory string includes a plurality of memory cell transistors connected in series between a string selection transistor and a ground selection transistor;

and

the determining determines whether either one of the ground selection transistor and the string selection transistor has deteriorated.

5. The method of claim 1, wherein

the currently programmed memory string includes a string selection transistor, at least a first dummy memory cell transistor, a plurality of memory cell transistors, at least a second dummy memory cell transistor, and a ground selection transistor connected in series;

and

the determining determines whether either one of the ground selection transistor and the string selection transistor has deteriorated.

6. The method of claim 1, further comprising:

performing the determining whether the selection transistor has deteriorated in response to a command.

7. The method of claim 6, wherein the command is one of a program command and a read command.

8. The method of claim 6, wherein the command is a verification command, which indicates to perform the determining.

9. The method of claim 6, further comprising:

receiving the command from a host.

10. The method of claim 6, further comprising:

receiving the command from a memory controller associated with the memory.

11. The method of claim 6, wherein the performing performs the determining whether the selection transistor has deteriorated before or after an operation associated with the command.

12. The method of claim 6, wherein the performing comprises:

generating a count value indicating a number of times the command is received;

triggering performance of the determining whether the selection transistor has deteriorated if the count value exceeds a reference value.

13. The method of claim 12, wherein the reference value is randomly generated.

14. The method of claim 12, wherein the triggering triggers the determining whether the selection transistor has deteriorated for at least one currently programmed memory string in a memory cluster which was most recently accessed based on the command.

15. The method of claim 6, wherein the performing comprises:

generating a count value indicating a number of times the command is received for a memory cluster including the currently programmed memory string; and

triggering performance of the determining whether the selection transistor has deteriorated if the count value exceeds a reference value.

16. The method of claim 1, further comprising:

performing the determining whether the selection transistor has deteriorated based on a wear level of a memory cluster including the currently programmed memory string.

17. The method of claim 1, further comprising:

determining whether a memory cluster is bad based on a number of memory strings in the memory cluster determined to be deteriorated; and

prohibiting access to the memory cluster if the memory cluster is determined to be bad.

18. The method of claim 1, wherein the memory is a vertical NAND.

19. A method of operating a nonvolatile memory device, the nonvolatile memory device including a plurality of memory cells formed to be perpendicular to a substrate and a plurality of cell strings being connected in common to a bit line, each of the plurality of cell strings includes serially-connected memory cells among the plurality of memory cells and a selection transistor, comprising:

applying a first selection voltage to a gate of a selection transistor of a cell string from among the plurality of cell strings;

determining a deterioration of the selection transistor based on whether the selection transistor is turned off; and

copying data programmed in memory cells of the cell string to memory cells of a different cell string.

20. The method of claim 19, wherein

the copying includes applying a second selection voltage greater than the first selection voltage to the gate of the selection transistor to turn on the selection transistor.