Migration between CPU cores
First Claim
1. A method comprising:
- processing, by a plurality of cores of a storage controller, one or more tasks and one or more interrupt service routines;
responsive to detecting a low system load, transitioning from a multi-core configuration to a single-core configuration, the transitioning including migrating the one or more tasks and one or more interrupt service routines from the plurality of cores to a target core by;
accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines;
identifying, based on the mapping, the target core that corresponds to the task and the interrupt service routine;
blocking the task from being processed by a source core in response to identifying the target core;
in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine;
in response to identifying the target core, assigning the task and the interrupt to the target core;
after assigning the interrupt to the target core, enabling the interrupt; and
after assigning the task to the target core, processing the task by the target core.
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Accused Products
Abstract
A method for migration of operations between CPU cores, the method includes: processing, by a source core, one or more tasks and one or more interrupt service routines; accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines; identifying, based on the mapping, a target core that corresponds to the task and the interrupt service routine; blocking the task from being processed by the source core in response to identifying the target core; in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine; in response to identifying the target core, assigning the task and the interrupt to the target core; after assigning the interrupt to the target core, enabling the interrupt; and after assigning the task to the target core, processing the task by the target core.
25 Citations
19 Claims
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1. A method comprising:
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processing, by a plurality of cores of a storage controller, one or more tasks and one or more interrupt service routines; responsive to detecting a low system load, transitioning from a multi-core configuration to a single-core configuration, the transitioning including migrating the one or more tasks and one or more interrupt service routines from the plurality of cores to a target core by; accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines; identifying, based on the mapping, the target core that corresponds to the task and the interrupt service routine; blocking the task from being processed by a source core in response to identifying the target core; in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine; in response to identifying the target core, assigning the task and the interrupt to the target core; after assigning the interrupt to the target core, enabling the interrupt; and after assigning the task to the target core, processing the task by the target core. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computing device comprising:
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a memory containing machine-readable medium comprising machine executable code having stored thereon instructions for performing a method of migrating tasks and interrupt service routines (ISRs) from a source core to a plurality of cores and from the plurality of cores to the source core; and a processor coupled to the memory, the processor configured to execute the machine executable code to cause the processor to; access a mapping; identify from the mapping, (1) a first set of tasks and a first set of ISRs to migrate to a first core of the plurality of cores, and (2) a second set of tasks and a second set of ISRs to migrate to a second core of the plurality of cores; perform the following operations according to identifying the first set of tasks and the first set of ISRs; block the first set of tasks and disable a first set of interrupts, wherein the first set of interrupts corresponds to the first set of ISRs; assign the first set of tasks and the first set of interrupts to the first core; and enable the first set of interrupts and unblock the first set of tasks; perform the following operations according to identifying the second set of tasks and the second set of ISRs; block the second set of tasks and disable a second set of interrupts, wherein the second set of interrupts corresponds to the second set of ISRs; assign the second set of tasks and the second set of interrupts to the second core; and enable the second set of interrupts and unblock the second set of tasks; and responsive to detecting a low system load, transition from a multi-core configuration to a single-core configuration, the transition including migrating the first set of tasks and the second set of tasks to the source core. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A non-transitory machine-readable medium having stored thereon instructions for performing a method comprising machine executable code that when executed by at least one machine, causes the machine to:
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during an initialization, execute a plurality of tasks and a plurality of interrupt service routines (ISRs) on a first core; after completing the initialization, migrate the plurality of tasks and the plurality of ISRs across a plurality of cores, including; accessing a mapping that associates the plurality of tasks and the plurality of ISRs with the plurality of cores; based on the mapping, assigning the plurality of tasks to the plurality of cores as assigned tasks; based on the mapping, assigning one or more interrupts to the plurality of cores as assigned interrupts, the one or more interrupts corresponding to the plurality of ISRs; handling the assigned interrupts on the plurality of cores; and executing the assigned tasks on the plurality of cores; and responsive to detecting a low system load, transition from a multi-core configuration to a single-core configuration, the transition including migrating the plurality of tasks and the plurality of ISRs from the plurality of cores to the first core. - View Dependent Claims (16, 17, 18, 19)
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Specification