Flash memory apparatus and storage management method for flash memory
First Claim
1. A flash memory apparatus, comprising:
- a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and
a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks;
wherein when completing program of the plurality of single-level-cell blocks, the flash memory module is arranged for performing an internal copy operation to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks.
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Abstract
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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Citations
16 Claims
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1. A flash memory apparatus, comprising:
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a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; wherein when completing program of the plurality of single-level-cell blocks, the flash memory module is arranged for performing an internal copy operation to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A flash memory storage management method, comprising:
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providing a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; classifying data to be programmed into a plurality of groups of data; respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; and when completing program of the plurality of single-level-cell blocks, performing an internal copy operation to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell block according to an order of storing data in the plurality of single-level-cell blocks. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification