Methods for cell phasing and placement in dynamic array architecture and implementation of the same

• US 9,910,950 B2
• Filed: 08/22/2016
• Issued: 03/06/2018
• Est. Priority Date: 03/07/2007
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Quandt, Jonathan R., Becker, Scott T., Gandhi, Dhrumil
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US15/243,748
• Publication Number:
  US 20160357897A1
• Time in Patent Office: 561 Days
• Field of Search: None
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Claims

1. A semiconductor chip, comprising:

a plurality of cells positioned in a side-by-side manner, the plurality of cells including linear-shaped conductive structures formed in a first chip level and linear-shaped conductive structures formed in a second chip level, the linear-shaped conductive structures formed in the first chip level oriented to extend lengthwise in a first direction, the linear-shaped conductive structures formed in the second chip level oriented to extend lengthwise in the first direction,

wherein the linear-shaped conductive structures in the first chip level are positioned in accordance with a first uniform pitch across the plurality of cells such that a distance as measured in a second direction perpendicular to the first direction between lengthwise centerlines of any two of the linear-shaped conductive structures in the first chip level is an integer multiple of the first uniform pitch,

wherein the linear-shaped conductive structures in the second chip level are positioned in accordance with a second uniform pitch across the plurality of cells such that a distance as measured in a second direction perpendicular to the first direction between lengthwise centerlines of any two of the linear-shaped conductive structures in the second chip level is an integer multiple of the second uniform pitch,

wherein each of the plurality of cells is configured in accordance with any one of an even integer number of possible phases, wherein each of the even integer number of possible phases for a given one of the plurality of cells is defined by a specific spatial relationship between the first uniform pitch locations in the first chip level and the second uniform pitch locations in the second chip level across the given one of the plurality of cells.

2. The semiconductor chip as recited in claim 1, wherein each of the possible phases for a given one of the plurality of cells is defined by a first index for the first chip level and a second index for the second chip level, wherein the first index corresponds to a first distance as measured in the second direction from a leftmost boundary of the given one of the plurality of cells to a first available position for placement of a linear-shaped conductive structure within the first chip level of the given one of the plurality of cells, and wherein the second index corresponds to a second distance as measured in the second direction from a leftmost boundary of the given one of the plurality of cells to a first available position for placement of a linear-shaped conductive structure within the second chip level of the given one of the plurality of cells.

3. The semiconductor chip as recited in claim 2, wherein the first index of each of the possible phases is equal to zero.

4. The semiconductor chip as recited in claim 2, wherein the first index of each of the possible phases is equal to either zero or one-half of the first uniform pitch.

5. The semiconductor chip as recited in claim 4, wherein the even integer number of possible phases is eight.

6. The semiconductor chip as recited in claim 5, wherein four times the first uniform pitch is equal to three times the second uniform pitch.

7. The semiconductor chip as recited in claim 6, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to five-sixths times the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-third times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to seven-sixths times the first uniform pitch,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to two-thirds times the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-sixth times the first uniform pitch,

wherein a seventh phase of the possible phases is defined by the first index equal to zero and by the second index equal to the first uniform pitch,

wherein an eighth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.

8. The semiconductor chip as recited in claim 6, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-sixth times the first uniform pitch,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-half times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to four-thirds times the first uniform pitch,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to five-sixths times the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-third times the first uniform pitch,

wherein a seventh phase of the possible phases is defined by the first index equal to zero and by the second index equal to seven-sixths times the first uniform pitch,

wherein an eighth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to two-thirds times the first uniform pitch.

9. The semiconductor chip as recited in claim 5, wherein four times the first uniform pitch is equal to five times the second uniform pitch.

10. The semiconductor chip as recited in claim 9, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to three-tenths times the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to three-fifths times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-tenth times the first uniform pitch,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to two-fifths times the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to seven-tenths times the first uniform pitch,

wherein a seventh phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-fifth times the first uniform pitch,

wherein an eighth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.

11. The semiconductor chip as recited in claim 4, wherein the even integer number of possible phases is four.

12. The semiconductor chip as recited in claim 11, wherein two times the first uniform pitch is equal to three times the second uniform pitch.

13. The semiconductor chip as recited in claim 12, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-sixth times the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-third times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.

14. The semiconductor chip as recited in claim 4, wherein the even integer number of possible phases is six.

15. The semiconductor chip as recited in claim 14, wherein three times the first uniform pitch is equal to two times the second uniform pitch.

16. The semiconductor chip as recited in claim 15, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-half times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to zero,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.

17. The semiconductor chip as recited in claim 14, wherein three times the first uniform pitch is equal to five times the second uniform pitch.

18. The semiconductor chip as recited in claim 17, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-tenth times the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-fifth times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to three-tenths times the first uniform pitch,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to two-fifths times the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.

19. The semiconductor chip as recited in claim 4, wherein the even integer number of possible phases is ten.

20. The semiconductor chip as recited in claim 19, wherein five times the first uniform pitch is equal to three times the second uniform pitch.

21. The semiconductor chip as recited in claim 20, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to seven-sixths times the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to two-thirds times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-sixth times the first uniform pitch,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to four-thirds times the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to five-sixth times the first uniform pitch,

wherein a seventh phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-third times the first uniform pitch,

wherein a eighth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to three-halves times the first uniform pitch,

wherein a ninth phase of the possible phases is defined by the first index equal to zero and by the second index equal to the first uniform pitch,

wherein a tenth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.

22. The semiconductor chip as recited in claim 19, wherein five times the first uniform pitch is equal to four times the second uniform pitch.

23. The semiconductor chip as recited in claim 22, wherein a first phase of the possible phases is defined by the first index equal to zero and by the second index equal to zero,

wherein a second phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to three-fourths times the first uniform pitch,

wherein a third phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-fourth times the first uniform pitch,

wherein a fourth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to the first uniform pitch,

wherein a fifth phase of the possible phases is defined by the first index equal to zero and by the second index equal to one-half times the first uniform pitch,

wherein a sixth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to zero,

wherein a seventh phase of the possible phases is defined by the first index equal to zero and by the second index equal to three-fourths times the first uniform pitch,

wherein a eighth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-fourth times the first uniform pitch,

wherein a ninth phase of the possible phases is defined by the first index equal to zero and by the second index equal to the first uniform pitch,

wherein a tenth phase of the possible phases is defined by the first index equal to one-half times the first uniform pitch and by the second index equal to one-half times the first uniform pitch.