Microprocessor with on-the-fly switching of decryption keys

• US 9,911,008 B2
• Filed: 10/15/2015
• Issued: 03/06/2018
• Est. Priority Date: 05/25/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Bean, Brent, Crispin, Thomas A.
• Primary Examiner(s): Rashid, Harunur
• Application Number:
  US14/884,547
• Publication Number:
  US 20160104011A1
• Time in Patent Office: 873 Days
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/54 by adding security routines or objects to programs
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2212/402 Encrypted data
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/20 Manipulating the length of blocks of bits, e.g. padding or block truncation
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/0827 involving distinctive intermediate devices or communication paths network architectures or network communication protocols using different networks H04L63/18
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/0891 : Revocation or update of secret information, e.g. encryption key update or rekeying
• CPC Class Codes: H04L 9/0894 : Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage

Abstract

A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.

Claims

1. A microprocessor comprising:

a secure memory configured to store and provide cryptographic keys for use in decrypting encrypted instructions; and

an instruction-processing pipeline configured to fetch instructions from a cache and execute them, the pipeline comprising;

a fetch unit configured to fetch both unencrypted and encrypted instructions of an instruction set architecture (ISA) supported by the microprocessor;

a decryption circuit configured to decrypt encrypted instructions using cryptographic keys received from the secure memory; and

one or more execution units configured to execute instructions or microinstructions translated from instructions;

wherein the ISA includes a store-key instruction to store one or more cryptographic keys into the secure memory, and wherein the microprocessor supports store-key instructions that are encrypted;

wherein when presented with an encrypted store-key instruction, the microprocessor is configured to use a first set of one or more cryptographic keys to decrypt the encrypted store-key instruction, and thereafter execute the decrypted store-key instruction, and thereafter use a second set of one or more cryptographic keys provided by the encrypted store-key instruction to decrypt a subsequent set of one or more encrypted instructions;

the microprocessor enabling an encrypted program to change the sets of cryptographic keys used to decrypt successive sets of the program'"'"'s instructions;

wherein the ISA includes a secure execution mode (SEM) instruction to request a switch from a normal execution mode into the SEM, and wherein the microprocessor is configured to prevent decryption of an encrypted program unless the microprocessor is in the SEM.

2. The microprocessor of claim 1, wherein the microprocessor is configured to condition granting the request to switch into SEM on the basis of whether the request is in the form of an instruction carrying an encrypted parameter, the instruction is part of a privileged program or process, and the encrypted parameter, when decrypted, meets a predetermined criteria for running the encrypted program.

3. The microprocessor of claim 2, wherein the encrypted parameter and encrypted program are encrypted using distinct cryptographic mechanisms.

4. The microprocessor of claim 1, wherein the store-key instruction holds the contents of one or more cryptographic keys in an immediate data field.

5. The microprocessor of claim 1, wherein the microprocessor is configured to execute decrypted instructions or microinstructions translated from decrypted instructions without making the decrypted instructions or microinstructions discoverable.

6. The microprocessor of claim 1, further comprising a processor bus, wherein the secure memory is inaccessible to the processor bus.

7. The microprocessor of claim 1, further comprising a cache memory hierarchy segregated from the secure memory.

8. The microprocessor of claim 1, further comprising an AES- or RSA-encrypted channel that enables writing of cryptographic key values to the secure memory.

9. The microprocessor of claim 1, wherein the secure memory is inaccessible to programs executing in a non-privileged execution mode.

10. A method of securely executing instructions in a microprocessor, the microprocessor for executing both unencrypted and encrypted instructions of an instruction set architecture (ISA) supported by the microprocessor, the method comprising:

storing a first set of one or more cryptographic keys for decrypting encrypted instructions into a secure memory;

fetching a first set of encrypted instructions;

decrypting the first set of encrypted instructions using the first set of one or more cryptographic keys;

fetching an encrypted store-key instruction to store a second set of one or more cryptographic keys for decrypting encrypted instructions into a secure memory;

decrypting the encrypted store-key instruction using the first set of one or more cryptographic keys;

executing the decrypted store-key instruction by storing the second set of one or more cryptographic keys into the secure memory;

fetching a second set of encrypted instructions; and

decrypting the second set of encrypted instructions using the second set of one or more cryptographic keys;

wherein the ISA includes a store-key instruction to store one or more cryptographic keys into the secure memory, and wherein the microprocessor supports store-key instructions that are encrypted;

wherein when presented with an encrypted store-key instruction, the microprocessor is configured to use a first set of one or more cryptographic keys to decrypt the encrypted store-key instruction, and thereafter execute the decrypted store-key instruction, and thereafter use a second set of one or more cryptographic keys provided by the encrypted store-key instruction to decrypt a subsequent set of one or more encrypted instructions, the microprocessor thereby enabling an encrypted program to change the sets of cryptographic keys used to decrypt successive sets of the program'"'"'s instructions; and

wherein the ISA includes a secure execution mode (SEM) instruction to request a switch from a normal execution mode into the SEM, and wherein the microprocessor is configured to prevent decryption of an encrypted program unless the microprocessor is in the SEM.

11. The method of claim 10, further comprising granting the request to switch into SEM on the basis of whether the request is in the form of an instruction carrying an encrypted parameter, the instruction is part of a privileged program or process, and the encrypted parameter, when decrypted, meets a predetermined criteria for running the encrypted program.

12. The method of claim 11, further comprising encrypting the encrypted parameter and encrypted program using distinct cryptographic mechanisms.

13. The method of claim 10, wherein the store-key instruction provides an immediate data field to hold the contents of one or more cryptographic keys.

14. The method of claim 10, further comprising writing of cryptographic key values to the secure memory via an AES- or RSA-encrypted channel.

15. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the microprocessor for executing both unencrypted and encrypted instructions of an instruction set architecture (ISA) supported by the microprocessor, the computer usable program code comprising;

first program code for specifying a secure memory configured to store and provide cryptographic keys for use in decrypting encrypted instructions; and

second program code for specifying an instruction-processing pipeline configured to fetch instructions from a cache and execute them, the pipeline comprising;

third program code for specifying a fetch unit configured to fetch both unencrypted and encrypted instructions of an instruction set architecture (ISA) supported by the microprocessor, wherein the ISA includes an store-key instruction to store one or more cryptographic keys into the secure memory, and wherein the microprocessor supports store-key instructions that are encrypted;

fourth program code for specifying a decryption circuit configured to decrypt encrypted instructions using cryptographic keys received from the secure memory; and

fifth program code for specifying one or more execution units configured to execute instructions or microinstructions translated from instructions; and

sixth program code for specifying a configuration of the microprocessor to respond to an encrypted store-key instruction by using a first set of one or more cryptographic keys to decrypt the encrypted store-key instruction, and thereafter executing the decrypted store-key instruction, and thereafter using a second set of one or more cryptographic keys provided by the encrypted store-key instruction to decrypt a subsequent set of one or more encrypted instructions;

wherein the ISA includes a store-key instruction to store one or more cryptographic keys into the secure memory, and wherein the microprocessor supports store-key instructions that are encrypted; and

wherein when presented with an encrypted store-key instruction, the microprocessor is configured to use a first set of one or more cryptographic keys to decrypt the encrypted store-key instruction, and thereafter execute the decrypted store-key instruction, and thereafter use a second set of one or more cryptographic keys provided by the encrypted store-key instruction to decrypt a subsequent set of one or more encrypted instructions, the microprocessor thereby enabling an encrypted program to change the sets of cryptographic keys used to decrypt successive sets of the program'"'"'s instructions; and

wherein the ISA includes a secure execution mode (SEM) instruction to request a switch from a normal execution mode into the SEM, and wherein the microprocessor is configured to prevent decryption of an encrypted program unless the microprocessor is in the SEM.