Secure field-programmable gate array (FPGA) architecture

• US 9,911,010 B2
• Filed: 08/15/2013
• Issued: 03/06/2018
• Est. Priority Date: 08/23/2010
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Woodall, Thomas R.
• Primary Examiner(s): Georgandellis, Andrew
• Application Number:
  US13/967,400
• Publication Number:
  US 20130332745A1
• Time in Patent Office: 1,664 Days
• Field of Search: 713189
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and system for configuring a field-programmable gate array (FPGA) includes receiving an encrypted FPGA load-decryption key at an FPGA from a remote key-storage device. The remote key-storage device may be external to and operatively connected with the FPGA. The encrypted FPGA load-decryption key is decrypted using a session key, which may be stored at both the FPGA and the remote key-storage device. Encrypted FPGA-configuration data is received at the FPGA, and decrypted and authenticated using the decrypted FPGA load-decryption key. The decryption of the FPGA-configuration data may indicate a cryptographic state associated with the FPGA-configuration data, which may be used in recurring authentication of the FPGA-configuration data. For recurring authentication, a challenge message may be received at the FPGA from an authentication device, which may be encrypted using the cryptographic state and the session key to generate a response message. The response message may then be sent to the authentication device to determine authenticity of the FPGA-configuration data.

Claims

1. A method of configuring a field-programmable gate array (FPGA), the method comprising:

receiving, at an FPGA, an encrypted FPGA load-decryption key from a remote key-storage device, wherein the remote key-storage device is external to and operatively connected with the FPGA;

calculating, at the FPGA, an entirety of an ephemeral session key;

decrypting the encrypted FPGA load-decryption key in a key-security unit using the ephemeral session key to provide a decrypted FPGA load-decryption key;

receiving encrypted FPGA-configuration data at the FPGA; and

decrypting and authenticating, in a configuration-data security unit, the FPGA-configuration data using the decrypted FPGA load-decryption key, and

further comprising;

obtaining an initialization vector from the FPGA-configuration data;

receiving a challenge message from an authentication device;

encrypting a challenge message using the initialization vector to generate a response message; and

sending the response message to the authentication device for an authenticity determination of the FPGA-configuration data.

2. The method of claim 1, wherein the initialization vector comprises a message authentication code.

3. method of claim 1, wherein the challenge message is received at the FPGA from an authentication device, the authentication device being external to the FPGA,

wherein the challenge message is encrypted in a state-encryption unit using the initialization vector to generate the response message, and

wherein the authentication device is arranged to compares the response message with an expected response message to indicate an authenticity of the FPGA-configuration data.

4. The method of claim 3, wherein obtaining an initialization vector from the FPGA-configuration data comprises performing a function on the FPGA-configuration data to obtain the initialization vector.

5. The method of claim 3, wherein obtaining an initialization vector from the FPGA-configuration data comprises extracting an initialization vector from the FPGA-configuration data.