Fast-bypass memory circuit

• US 9,911,470 B2
• Filed: 04/13/2012
• Issued: 03/06/2018
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kottapalli, Venkata, Pitkethly, Scott, Klingner, Christian, Gerlach, Matthew
• Primary Examiner(s): Tran, Uyen B
• Application Number:
  US13/447,037
• Publication Number:
  US 20130155783A1
• Time in Patent Office: 2,153 Days
• Field of Search: 365 4911, 365 76, 365 77, 365 78, 365189011, 36518902, 36518905, 36523001, 36523008, 3652331
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.

Claims

1. A memory circuit that presents input data at a data output promptly on receiving a clock pulse, the circuit comprising:

upstream memory logic configured to latch the input data on receiving the clock pulse;

downstream memory logic configured to store the latched input data; and

selection logic configured to indicate whether the upstream memory logic has latched the input data.

2. The memory circuit of claim 1 further comprising a buffer through which the clock pulse is received, delayed, in the upstream memory logic.

3. The memory circuit of claim 1 where the upstream memory logic comprises a clocked, sense-amplifier-type latch.

4. The memory circuit of claim 1 where an output of the upstream memory logic reveals whether the input data is latched, and where that output is presented to the selection logic.

5. The memory circuit of claim 4 where the output of the upstream memory logic includes first and second control lines complementary to each other when the input data is latched, and equal to each other when the input data is not latched, and where the first control line assumes the logic level of the input data when the input data is latched.

6. The memory circuit of claim 1 where the upstream memory logic, the downstream memory logic, and the selection logic are fabricated from complementary metal-oxide-semiconductor elements.

7. The memory circuit of claim 1 where the upstream memory logic is configured to present the latched input data to the selection logic, where the selection logic is configured to present the exposed logic level to the downstream memory logic, and where the downstream memory logic is configured to store the logic level exposed by the selection logic and to present the stored logic level at the data output.

8. The memory circuit of claim 7 where the clock pulse is received in the downstream memory logic before it is received in the upstream memory logic.

9. The memory circuit of claim 1 where the downstream memory logic is a clocked latch, and where an inverted output of the downstream memory logic drives the data output.

10. The memory circuit of claim 1 where the selection logic includes an inverter and an and-or-invert structure.

11. The memory circuit of claim 1 where the stored logic level presented at the data output is held until receipt of the clock pulse in the downstream memory logic.

12. The memory circuit of claim 1 where the upstream memory logic is configured to present the latched input data to the downstream memory logic, where the downstream memory logic is configured to present the stored, latched input data to the selection logic, and where the selection logic is configured to present the exposed logic level at the data output.

13. The memory circuit of claim 12 where the clock pulse is received in the selection logic before it is received in the upstream memory logic.

14. The memory circuit of claim 12 where the upstream memory logic and the downstream memory logic are coupled in a flip-flop.

15. The memory circuit of claim 12 where the selection logic includes one of a multiplexer and an inverting complex gate.

16. The memory circuit of claim 12 where the exposed logic level presented at the data output is held until receipt of the clock pulse in the selection logic.

17. A method to present input data at a data output of a memory circuit promptly on receiving a clock pulse in the memory circuit, the method comprising:

delaying receipt of the clock pulse in upstream memory logic of the memory circuit;

latching the input data in the upstream memory logic on receiving the clock pulse in the upstream memory logic; and

in a selection logic of the memory circuit, exposing a logic level derived from the input data before the input data is latched in the upstream memory logic, and, exposing a logic level derived from the latched input data after the input data is latched in the upstream memory logic.

18. The method of claim 17 further comprising:

presenting the latched input data of the upstream memory logic to the selection logic;

presenting the exposed logic level of the selection logic to the downstream memory logic;

storing the logic level exposed by the selection logic in downstream memory logic; and

presenting the stored logic level of the downstream memory logic to the data output.

19. The method of claim 17 further comprising determining based on an output of the upstream memory logic whether the input data is latched.

20. A memory circuit that presents input data at a data output promptly on receiving a clock pulse, the circuit comprising:

upstream memory logic configured to latch the input data on receiving the clock pulse;

selection logic configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched;

downstream memory logic configured to store the logic level exposed by the selection logic and to present the stored logic level at the data output on receiving the clock pulse; and

a buffer configured to delay receipt of the clock pulse in the upstream memory logic relative to receipt of the clock pulse in the downstream memory logic.