Method and system for storing and recovering data from flash memory

• US 9,911,487 B2
• Filed: 06/30/2015
• Issued: 03/06/2018
• Est. Priority Date: 05/19/2015
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Inventors: Nieuwejaar, Nils, Bonwick, Jeffrey S.
• Primary Examiner(s): Bradley, Matthew
• Application Number:
  US14/754,838
• Publication Number:
  US 20160343429A1
• Time in Patent Office: 980 Days
• Field of Search: 711103
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

Embodiments of the technology relate to storing user data and metadata in persistent storage in the event of a power failure and then recovering such stored data and metadata when power is restored.

Claims

1. A method for storing data, comprising:

writing a frag to an open data page in vaulted memory, wherein the open data page comprises a first table of contents (TOC) bit and a first physical address;

writing a first table of contents entry (TE) for the frag to an open TOC page in the vaulted memory, wherein the open TOC page comprises a second TOC bit, a second physical address, and a second TE;

receiving an event notification of a power failure for a storage module in which the vaulted memory is located;

in response to the event notification;

writing the frag to a page in a solid state memory module in the storage module, wherein the page is not associated with the first physical address; and

writing the first TE and the second TE to a second page in the solid state memory module, wherein the second page is not associated with the second physical address;

after powering on the storage module;

loading contents of the page and the second page from the solid state memory module into a memory of a control module;

identifying the first TE in the memory;

determining a third physical address based on the second physical address and at least a portion of the first TE;

determining, using the third physical address, that the frag is located in the memory;

initiating the writing of the frag to a fourth physical address in one selected from a group consisting of the solid state memory module and another solid state memory module.

2. The method of claim 1, further comprising:

after powering on the storage module;

identifying the second TE in the memory;

determining a fourth physical address based the second physical address and at least a portion of the second TE;

determining, using the fourth physical address, that a second frag associated with the fourth physical address is not located in the memory;

initiating a garbage collection operation to relocate the second frag to another location in one selected from a group consisting of the solid state memory module and another solid state memory module.

3. The method of claim 2, wherein the page and the second page are associated with a reserved portion of the solid state memory module and wherein the second frag is stored in a third page in the solid state memory module, wherein the third page is associated with a non-reserved portion of the solid state memory module.

4. The method of claim 3, wherein the solid state memory module is flash memory, wherein the reserved portion is operating in single-level cell (SLC) mode, and wherein the non-reserved portion is operating in multi-level cell (MLC) mode.

5. The method of claim 1, wherein the page and the second page are associated with a reserved portion of the solid state memory module.

6. The method of claim 1, wherein the solid state memory module is flash memory and wherein the reserved portion is operating in single-level cell (SLC) mode.

7. The method of claim 1, wherein the page and the second page are least significant bit (LSB) pages the solid state memory module.

8. A non-transitory computer readable medium for storing data comprising computer readable program code for:

writing a frag to an open data page in vaulted memory, wherein the open data page comprises a first table of contents (TOC) bit and a first physical address;

writing a first table of contents entry (TE) for the frag to an open TOC page in the vaulted memory, wherein the open TOC page comprises a second TOC bit, a second physical address, and a second TE;

receiving an event notification of a power failure for a storage module in which the vaulted memory is located;

in response to the event notification;

writing the frag to a page in a solid state memory module in the storage module, wherein the page is not associated with the first physical address; and

writing the first TE and the second TE to a second page in the solid state memory module, wherein the second page is not associated with the second physical address;

after powering on the storage module;

loading contents of the page and the second page from the solid state memory module into a memory of a control module;

identifying the first TE in the memory;

determining a third physical address based on the second physical address and at least a portion of the first TE;

determining, using the third physical address, that the frag is located in the memory;

initiating the writing of the frag to a fourth physical address in one selected from a group consisting of the solid state memory module and another solid state memory module.

9. The non-transitory computer readable medium of claim 8, further comprising computer readable program code for:

after powering on the storage module;

identifying the second TE in the memory;

determining a fourth physical address based the second physical address and at least a portion of the second TE;

determining, using the fourth physical address, that a second frag associated with the fourth physical address is not located in the memory;

initiating a garbage collection operation to relocate the second frag to another location in one selected from a group consisting of the solid state memory module and another solid state memory module.

10. The non-transitory computer readable medium of claim 9, wherein the page and the second page are associated with a reserved portion of the solid state memory module and wherein the second frag is stored in a third page in the solid state memory module, wherein the third page is associated with a non-reserved portion of the solid state memory module.

11. The non-transitory computer readable medium of claim 10, wherein the solid state memory module is flash memory, wherein the reserved portion is operating in single-level cell (SLC) mode, and wherein the non-reserved portion is operating in multi-level cell (MLC) mode.

12. The non-transitory computer readable medium of claim 8, wherein the page and the second page are least significant bit (LSB) pages the solid state memory module.

13. A method for storing data, comprising:

writing a frag to an open data page in vaulted memory, wherein the open data page comprises a first table of contents (TOC) bit and a first physical address;

writing a first table of contents entry (TE) for the frag to an open TOC page in the vaulted memory, wherein the open TOC page comprises a second TOC bit, a second physical address, and a second TE;

receiving an event notification of a power failure for a storage module in which the vaulted memory is located;

in response to the event notification;

writing the frag to a page in a solid state memory module in the storage module, wherein the page is not associated with the first physical address; and

writing the first TE and the second TE to a second page in the solid state memory module, wherein the second page is not associated with the second physical address;

after powering on the storage module;

loading contents of the page and the second page from the solid state memory module into a memory of a control module;

identifying the second TE in the memory;

determining a third physical address based on the second physical address and at least a portion of the second TE;

determining, using the third physical address, that a second frag associated with the third physical address is not located in the memory;

initiating a garbage collection operation to relocate the second frag to another location in one selected from a group consisting of the solid state memory module and another solid state memory module.

14. The method of claim 13, wherein the page and the second page are associated with a reserved portion of the solid state memory module and wherein the second frag is stored in a third page in the solid state memory module, wherein the third page is associated with a non-reserved portion of the solid state memory module.

15. The method of claim 14, wherein the solid state memory module is flash memory, wherein the reserved portion is operating in single-level cell (SLC) mode, and wherein the non-reserved portion is operating in multi-level cell (MLC) mode.

16. The method of claim 13, wherein the page and the second page are associated with a reserved portion of the solid state memory module.

17. The method of claim 13, wherein the solid state memory module is flash memory and wherein the reserved portion is operating in single-level cell (SLC) mode.

18. The method of claim 13, wherein the page and the second page are least significant bit (LSB) pages the solid state memory module.