Three-dimensional vertical NOR flash thin-film transistor strings

• US 9,911,497 B1
• Filed: 10/13/2017
• Issued: 03/06/2018
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/783,201
• Time in Patent Office: 144 Days
• Field of Search: 36518501-18533
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 : Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6675 : Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

Claims

1. A process for creating a memory structure, comprising:

forming in and on a semiconductor substrate circuitry for supporting a memory circuit, the semiconductor substrate having a planar surface;

providing a first insulation layer over the planar surface of the semiconductor substrate;

providing contacts in the first insulation layer extending in a first direction through the first insulation layer for electrically connecting the circuitry in and on the semiconductor substrate, the first direction being substantially orthogonal to the planar surface of the semiconductor substrate;

forming a plurality of stacks of conductors, each conductor in each stack extending lengthwise substantially in a second direction parallel to the planar surface of the semiconductor substrate, the conductors in each stack being isolated from each other by intervening insulation layers, the stacks of conductors being separated from each other by a plurality of trenches, the plurality of trenches being arrayed substantially in rows along the second direction and in rows along a third direction parallel to the planar surface of the semiconductor substrate and reaching along the first direction to the first insulation layer;

depositing a charge-trapping layer over the sidewalls and over the bottom of the trenches;

removing both the charge trapping layer from the bottom of the trenches and the first insulation layer underneath the charge trapping layer, thereby exposing portions of the substrate;

depositing a lightly doped polysilicon over the surface of the charge-trapping layers on the sidewalls of the trenches and extending down to the exposed portions of the substrate;

filling the trenches with a fast-etching dielectric layer;

photo-lithographical patterning and anisotropically etching the fast-etching dielectric layer to form shafts that reach the first insulation layer and which exposes portions of the lightly doped polysilicon;

providing a layer of heavily doped polysilicon on the sidewalls of the shafts adjacent the exposed portions of the lightly doped polysilicon; and

removing the heavily doped polysilicon from the top of the conductor stacks and providing a second insulation layer over the conductor stacks.

2. The process of claim 1, wherein depositing the lightly doped polysilicon comprises depositing an amorphous silicon and subsequently annealing the amorphous silicon to form a polycrystalline silicon.

3. The process of claim 1, wherein the layer of heavily doped polysilicon is provided to substantially fill the shafts.

4. The process of claim 1, wherein the conductors comprise a material selected from a group of low resistivity materials consisting of tungsten or another refractive metal, N+ doped polysilicon, P+ doped polysilicon, nickel silicide, cobalt silicide, and tungsten or other silicides and salicides of heavily doped polysilicon, and combinations thereof.

5. The process of claim 1, wherein the lightly doped polysilicon is of a first conductivity and wherein the heavily doped polysilicon is of an opposite conductivity to the first conductivity.

6. The process of claim 1, wherein the memory structure comprises a plurality of thin film transistors organized as a vertical NOR string, and wherein the heavily doped polysilicon in adjacent shafts provide respectively a shared vertical source line and a shared vertical local drain or bit line for the vertical NOR string, the lightly doped polysilicon forms a shared channel structure, and the stack of conductors form separate word lines for the thin film transistors in the vertical NOR string.

7. The process of claim 6, wherein one or more dummy conductors are formed to further increase the parasitic capacitance of the shared vertical source line.

8. The process of claim 1, wherein forming the plurality of stack of conductors comprises:

forming a plurality of conductor layers, each conductor layer being substantially parallel to the planar surface of the semiconductor substrate, the conductor layers being isolated from each other by the intervening insulation layers; and

photo-lithographical patterning and anisotropically etching the conductor layers and the intervening insulation layers to form the plurality of trenches.

9. The process of claim 8, wherein each successive conductor layer of the plurality of conductor layers extends a lesser distance along the third direction than its immediately previous conductor layer.

10. The process of claim 9 wherein, after all conductor layers are formed, etching vias through the intervening insulation layers previously formed to connect each conductor layer to the semiconductor substrate circuitry.

11. The process of claim 8, wherein the conductor layers are patterned to form conductive strips extending lengthwise along the third direction, and such that a distance between adjacent conductor strips of the same conductor layer at predetermined locations along their lengths are less than twice as thick as the charge-trapping layer.

12. The process of claim 8, wherein the conductor layers are patterned to conductive strips extending lengthwise along the third direction, and such that predetermined sections in each conductive strip have a predetermined concave radius of curvature.

13. The process of claim 1, wherein forming the plurality of stacks of conductors comprises:

providing a plurality of insulation layers as the intervening insulation layers, the insulation layers being separated from each other by intervening sacrificial layers;

providing a mechanical support structure for the insulating layers;

removing the sacrificial layers formed between the insulating layers to create cavities between the insulating layers while the mechanical support structure maintains the separation between the insulating layers; and

filling the cavities with high conductivity conductors.

14. The process of claim 13, wherein the cavities and conductors are formed following deposition of the charge-trapping layer over the sidewalls of the trenches and deposition of the lightly doped polysilicon over the surface of the charge-trapping layer.

15. The process of claim 13, wherein the insulation layers comprise silicon dioxide and the sacrificial layers comprise silicon nitride or other fast-etching materials with high selectivity to the insulation layers and the charge trapping layers.

16. The process of claim 1, further comprising depositing, photo-lithographically patterning and etching an interconnect conductor layer over the first insulation layer.

17. The process of claim 16, further comprising providing active material between the interconnect conductor layer and the heavily doped polysilicon to form access selection transistors connecting the interconnect conductor layer and the heavily doped polysilicon.

18. The process of claim 1, wherein the charge-trapping material comprises a blocking layer, a storage layer and a tunnel dielectric layer.

19. The process of claim 18, wherein the blocking layer comprises one or more films of aluminum oxide, hafnium oxide, silicon dioxide, silicon nitride or a combination thereof.

20. The process of claim 18, wherein the storage layer comprises one or more films of silicon nitride, silicon-rich oxynitride, conductive nanodots embedded in a dielectric film, isolated floating gates, or a combination thereof.

21. The process of claim 18, wherein the tunnel dielectric layer comprises a silicon dioxide film, or a silicon oxide-silicon nitride-silicon oxide (“

ONO”

) triple-layer.

22. The process of claim 18, wherein the blocking layer, the storage layer and the tunnel dielectric layer have thicknesses no greater than 15 nanometers, 10 nanometers and 10 nanometers, respectively.

23. The process of claim 18, wherein the tunnel dielectric layer comprises a silicon oxide film or a silicon nitride film of thickness 4 nanometers or less.

24. The process of claim 21, wherein the ONO triple-layer is 6-25 nanometers thick.

25. The process of claim 1, wherein the lightly-doped polysilicon has a doping concentration between 1.0×

10¹⁶ and 8.0×

10¹⁸.