Method of processing a semiconductor device

• US 9,911,627 B1
• Filed: 04/17/2013
• Issued: 03/06/2018
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Sekar, Deepak
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US13/864,244
• Time in Patent Office: 1,784 Days
• Field of Search: 438122
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/098 : the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power distribution grid to provide power to the first transistors, processing a second layer overlying the first transistors and including second transistors, where the second layer includes a through layer via with diameter of less than 150 nm, forming a second power distribution grid overlaying the second transistors, where the first power distribution grid includes first power conductors and the second power distribution grid includes second power conductors, and where the second power conductors are substantially wider or thicker than the first power conductors, and where the device includes a plurality of vias to connect the second power distribution grid to the first power distribution grid.

Claims

1. A method for processing a 3D semiconductor device, the method comprising:

processing a first layer comprising first transistors,

forming a first power distribution grid to provide power to said first transistors,

processing a second layer overlying said first transistors and comprising second transistors,

wherein said second layer has a thickness greater than 5 nm and less than 2 microns,

forming a second power distribution grid overlaying said second transistors,

wherein said first power distribution grid comprises first power conductors and said second power distribution grid comprises second power conductors, and

wherein said second power conductors are substantially wider or thicker than said first power conductors, and

wherein said device comprises a plurality of vias to connect said second power distribution grid to said first power distribution grid.

2. The method according to claim 1, further comprising:

forming a thermal connection path from said second layer to a top or bottom surface of said device,

wherein said thermal connection path has a thermal conductivity greater than 10 W/m-K.

3. The method according to claim 1, further comprising:

forming a heat-spreader layer between said first layer and said second layer, wherein

said heat-spreader layer comprises a thermal conductivity greater than 10 W/m-K.

4. The method according to claim 1, further comprising:

forming a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

5. The method according to claim 1, further comprising:

forming at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.

6. The method according to claim 1,

wherein said through layer via is part of a heat removal structure of said device.

7. The method according to claim 1, further comprising:

forming a power distribution network to provide power to said second transistors,

wherein said device comprises a heat removal path between said power distribution network and a top or bottom surface of said device.

8. A method for processing a 3D semiconductor device, the method comprising:

processing a first layer comprising first transistors,

processing a second layer overlying said first transistors and comprising second transistors,

wherein said second layer has a thickness greater than 5 nm and less than 2 microns,

wherein said first layer comprises at least one first circuit comprising said first transistors, said at least one first circuit is circumscribed by a first guard ring,

wherein said second layer comprises at least one second circuit comprising said second transistors, said at least one second circuit is circumscribed by a second guard ring, and

wherein said second guard ring overlays said first guard ring wherein said second dice lane is overlaying and aligned to said first dice lane, and wherein said aligned is misaligned less than 200 nm,

wherein said second dice lane is overlaying and aligned to said first dice lane, and

wherein said aligned is misaligned less than 40 nm.

9. The method according to claim 8, further comprising:

forming a thermal connection path from said second layer to a top or bottom surface of said device,

wherein said thermal connection path has a thermal conductivity greater than 10 W/m-K.

10. The method according to claim 8, further comprising:

forming a heat-spreader layer between said first layer and said second layer, wherein

said heat-spreader layer comprises a thermal conductivity greater than 10 W/m-K.

11. The method according to claim 8, further comprising:

forming a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

12. The method according to claim 8, further comprising:

forming at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.

13. The method according to claim 8,

wherein said through layer via is part of a heat removal structure of said device.

14. The method according to claim 8, further comprising:

forming a power distribution network to provide power to said second transistors,

wherein said device comprises a heat removal path between said power distribution network and a top or bottom surface of said device.

15. A method for processing a 3D semiconductor device, the method comprising:

processing a first layer comprising first transistors,

processing a second layer overlying said first transistors and comprising second transistors,

wherein said second layer has a thickness greater than 5 nm and less than 2 microns,

wherein a portion of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no conductive connections to said portion of said first transistors that cross said first dice lane;

wherein a portion of said second transistors is circumscribed by a second dice lane of at least 10 microns width, and there are no conductive connections to said portion of second transistors that cross said second dice lane,

wherein said second dice lane is overlaying and aligned to said first dice lane, and

wherein said aligned is misaligned less than 200 nm.

16. The method according to claim 15, further comprising:

forming a thermal connection path from said second layer to a top or bottom surface of said device,

wherein said thermal connection path has a thermal conductivity greater than 10 W/m-K.

17. The method according to claim 15, further comprising:

forming a heat-spreader layer between said first layer and said second layer, wherein

said heat-spreader layer comprises a thermal conductivity greater than 10 W/m-K.

18. The method according to claim 15, further comprising:

forming a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

19. The method according to claim 15, further comprising:

forming at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.

20. The method according to claim 15,

wherein said through layer via is part of a heat removal structure of said device.