Process for making and using mesh-style NCEM pads

• US 9,911,649 B1
• Filed: 09/08/2016
• Issued: 03/06/2018
• Est. Priority Date: 02/03/2015
• Status: Expired due to Fees

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US15/259,309
• Time in Patent Office: 544 Days
• Field of Search: 438 11- 18, 257 48
• CPC Class Codes: G01N 23/2251 using incident electron beams, e.g. scanning electron microscopy [SEM]
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, and may include NCEM pads that comprise a mesh of GATECNT and AACNT stripes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Claims

1. A method for processing a semiconductor substrate, comprising at least the following steps:

using one or more mask(s) to pattern a plurality of adjacent source/drain contact (AACNT) stripes on the substrate;

using one or more mask(s) to pattern a plurality of adjacent gate contact (GATECNT) stripes on the substrate;

wherein the GATECNT stripes perpendicularly intersect the AACNT stripes to form a mesh-style non-contact electrical measurement (NCEM) pad; and

after forming the NCEM pad, obtaining in-line NCEM from the mesh-style NCEM pad.

2. A method for processing a semiconductor substrate, as defined in claim 1, further comprising at least the following additional steps:

using one or more mask(s) to pattern a plurality of via to interconnect stack (V0) vias above at least some of the GATECNT and/or AACNT stripes of the mesh-style NCEM pad; and

,

using one or more mask(s) to pattern one or more first wiring layer (M1) features above one or more of said V0 vias to form an M1 NCEM pad.

3. A method for processing a semiconductor substrate, as defined in claim 2, further comprising at least the following additional step:

obtaining in-line NCEM from the M1 NCEM pad.