Methods for forming germanium and silicon germanium nanowire devices

• US 9,911,660 B2
• Filed: 04/26/2016
• Issued: 03/06/2018
• Est. Priority Date: 04/26/2016
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Yoon, Hyungsuk Alexander, Zhu, Zhongwei
• Primary Examiner(s): Seven, Evren
• Application Number:
  US15/138,796
• Publication Number:
  US 20170309521A1
• Time in Patent Office: 679 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method for forming nanowire semiconductor devices includes a) providing a substrate including an oxide layer defining vias; and b) depositing nanowires in the vias. The nanowires are made of a material selected from a group consisting of germanium or silicon germanium. The method further includes c) selectively etching back the oxide layer relative to the nanowires to expose upper portions of the nanowires; and d) doping the exposed upper portions of the nanowires using a dopant species.

Claims

1. A method for forming nanowire semiconductor devices, comprising:

a) providing a substrate including an oxide layer defining vias;

b) growing nanowires in the vias, wherein the nanowires are made of a material selected from a group consisting of germanium or silicon germanium;

c) selectively etching back the oxide layer relative to the nanowires to expose upper portions of the nanowires; and

d) doping the exposed upper portions of the nanowires using a dopant species.

2. The method of claim 1, further comprising:

e) annealing the substrate.

3. The method of claim 1, wherein the nanowires are single-crystalline.

4. The method of claim 1, wherein the substrate includes:

a silicon layer,

wherein the oxide layer is deposited on the silicon layer and the oxide layer is patterned to define the vias.

5. The method of claim 1, further comprising:

e) depositing gate dielectric layers on the exposed upper portions of the nanowires.

6. The method of claim 5, further comprising:

f) depositing oxide film on the substrate to perform gap fill; and

g) performing chemical mechanical polishing of the oxide film.

7. The method of claim 6, further comprising:

h) defining masked and unmasked areas in the oxide film, wherein the unmasked areas are located adjacent to gate areas corresponding to the gate dielectric layers; and

i) etching the unmasked areas to create gate openings.

8. The method of claim 7, further comprising:

j) performing metallization to fill the gate openings with gate metal; and

k) performing chemical mechanical polishing on the gate metal.

9. The method of claim 1, wherein the doping in d) is performed using a process selected from a group consisting of a plasma process and an atomic layer deposition (ALD) process.

10. The method of claim 5, wherein depositing gate dielectric layers in e) is performed using an atomic layer deposition (ALD) process.