‘RDL-First’ packaged microelectronic device for a package-on-package device

• US 9,911,718 B2
• Filed: 11/16/2016
• Issued: 03/06/2018
• Est. Priority Date: 11/17/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Prabhu, Ashok S., Katkar, Rajesh
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US15/353,552
• Publication Number:
  US 20170141042A1
• Time in Patent Office: 475 Days
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/54 Providing fillings in containers, e.g. gas fillings
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/18 : Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15322 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, at least one redistribution layer includes first interconnect pads on a lower surface and second interconnect pads on an upper surface of the at least one redistribution layer. Interconnect structures are on and extend away from corresponding upper surfaces of the second interconnect pads. A microelectronic device is coupled to an upper surface of the at least one redistribution layer. A dielectric layer surrounds at least portions of shafts of the interconnect structures. The interconnect structures have upper ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

Claims

1. A method for forming a packaged microelectronic device, comprising:

forming at least one redistribution layer having an inner region and an outer region outside the inner region;

the forming of the at least one redistribution layer comprising forming first interconnect pads in both the inner region and the outer region at a lower surface and second interconnect pads in the outer region at an upper surface of the at least one redistribution layer;

forming interconnect structures on and extending away from corresponding upper surfaces of the second interconnect pads in the outer region;

coupling a microelectronic device to an upper surface of the at least one redistribution layer in the inner region;

forming a reinforcing layer with a stiffener material on the interconnect structures;

forming a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device; and

the interconnect structures having upper ends thereof protruding above an upper surface of the dielectric layer a distance.

2. The method according to claim 1, wherein the forming of the at least one redistribution layer comprises:

obtaining a carrier substrate having an upper surface and a lower surface opposite the upper surface;

adhering an adhesive layer to the upper surface of the carrier substrate;

applying a metal layer to an upper surface of the adhesive layer; and

patterning the first interconnect pads out of the metal layer including forming an area array layout for a subset of the first interconnect pads in the inner region.

3. The method according to claim 2, wherein:

the metal layer is a metal foil; and

the adhesive layer is an adhesive tape.

4. The method according to claim 1, wherein the interconnect structures include plating-formed posts plated in part on the upper surfaces of the second interconnect pads.

5. The method according to claim 1, wherein the interconnect structures include wire bond wires bonded to the upper surfaces of the second interconnect pads.

6. The method according to claim 1, wherein the interconnect structures are first interconnect structures, the packaged microelectronic device further comprising:

forming second interconnect structures on and extending away from an upper surface of the microelectronic device;

the forming of the dielectric layer including surrounding at least portions of shafts of the second interconnect structures; and

the second interconnect structures having upper ends thereof protruding above the upper surface of the dielectric layer the distance.

7. The method according to claim 6, wherein the packaged device is a first packaged device, the method further comprising coupling a second packaged microelectronic device to the protrusions of the first and the second interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

8. The method according to claim 1, wherein the packaged device is a first packaged device, the method further comprising coupling a second packaged microelectronic device to the protrusions of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

9. The method according to claim 1, wherein the upper ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding bases of the interconnect structures.

10. The method according to claim 1, wherein portions of the stiffener material wick-up at least a portion of the interconnect structures.

11. A packaged microelectronic device, comprising:

at least one redistribution layer having an inner region and an outer region outside the inner region;

the at least one redistribution layer comprising first interconnect pads in both the inner region and the outer region on a lower surface and second interconnect pads in the outer region on an upper surface of the at least one redistribution layer;

interconnect structures on and extending away from corresponding upper surfaces of the second interconnect pads in the outer region;

a microelectronic device coupled to an upper surface of the at least one redistribution layer in the inner region;

a reinforcing layer formed with a stiffener material on the interconnect structures;

a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device; and

the interconnect structures having upper ends thereof protruding above an upper surface of the dielectric layer a distance.

12. The packaged microelectronic device according to claim 11, wherein the first interconnect pads include an area array layout for a subset of the first interconnect pads in the inner region.

13. The packaged microelectronic device according to claim 11, wherein the interconnect structures include plating-formed posts plated in part on the upper surfaces of the second interconnect pads.

14. The packaged microelectronic device according to claim 11, wherein the interconnect structures include wire bond wires bonded to the upper surfaces of the second interconnect pads.

15. The packaged microelectronic device according to claim 11, wherein the interconnect structures are first interconnect structures, the packaged microelectronic device further comprising:

second interconnect structures on and extending away from an upper surface of the microelectronic device;

the dielectric layer formed to surround at least portions of shafts of the second interconnect structures; and

the second interconnect structures having upper ends thereof protruding above the upper surface of the dielectric layer the distance.

16. The packaged microelectronic device according to claim 11, wherein the packaged microelectronic device is a first packaged microelectronic device, the first packaged microelectronic device being coupled to a second packaged microelectronic device, the second packaged microelectronic device coupled to the protrusions of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

17. The packaged microelectronic device according to claim 11, wherein the upper ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding bases of the interconnect structures.

18. The packaged microelectronic device according to claim 11, wherein:

portions of the stiffener material wick-up at least portions of the interconnect structures; and

the stiffener material is a polymeric material.