Display device

• US 9,911,762 B2
• Filed: 11/29/2016
• Issued: 03/06/2018
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: Yan, Tzu-Min, Lin, Ming-Chang, Lee, Kuan-Feng
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US15/363,289
• Publication Number:
  US 20170162606A1
• Time in Patent Office: 462 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display device is provided, which includes a substrate structure containing a substrate with a pixel region, and the pixel region includes an aperture region. A metal oxide semiconductor transistor is disposed over the substrate and includes a metal oxide semiconductor layer with a first channel region, a first gate electrode corresponding to the first channel region, and a silicon oxide insulating layer on the metal oxide semiconductor layer. The silicon oxide insulating layer includes an opening corresponding to the aperture region. A polysilicon transistor is disposed over the substrate. The display device also includes an opposite substrate structure, and a display medium between the substrate structure and the opposite substrate structure.

Claims

1. A display device, comprising:

a substrate structure, comprising;

a substrate including a pixel region, and the pixel region including an aperture region;

a metal oxide semiconductor transistor disposed over the substrate and comprising;

a metal oxide semiconductor layer including a first channel region,

a first gate electrode under the first channel region; and

a silicon oxide insulating layer disposed over the metal oxide semiconductor layer, wherein the silicon oxide insulating layer includes a first opening overlapping the aperture region; and

a polysilicon transistor disposed over the substrate;

an opposite substrate structure; and

a display medium disposed between the substrate structure and the opposite substrate structure,

wherein the metal oxide semiconductor transistor further comprises a gate insulating layer disposed between the metal oxide semiconductor layer and the first gate electrode, the gate insulating layer comprises a first silicon oxide layer, and the first silicon oxide layer has a second opening overlapping the aperture region.

2. The display device as claimed in claim 1, wherein the polysilicon transistor is arranged in a driving circuit of the substrate structure, the metal oxide semiconductor transistor is arranged in the pixel region, and the polysilicon transistor is electrically connected to the metal oxide semiconductor transistor.

3. The display device as claimed in claim 1, wherein the polysilicon transistor comprises:

a polysilicon layer including a second channel region; and

a second gate electrode on the second channel region,

wherein the polysilicon layer is disposed between the substrate and the second gate electrode, and the metal oxide semiconductor layer is disposed over the first gate electrode.

4. The display device as claimed in claim 3, wherein the substrate structure further comprises a light shielding layer disposed between the polysilicon layer and the substrate.

5. The display device as claimed in claim 4, wherein the first gate electrode is disposed between the metal oxide semiconductor layer and the substrate, and the first gate electrode and the light shielding layer are the same layer.

6. The display device as claimed in claim 3, wherein the polysilicon transistor further comprises an amorphous silicon layer disposed over the polysilicon layer.

7. The display device as claimed in claim 1, wherein the substrate structure further comprises a silicon nitride insulating layer disposed over the metal oxide semiconductor transistor and the polysilicon transistor, wherein the silicon nitride insulating layer directly contacts with the substrate in the aperture region.

8. The display device as claimed in claim 1, wherein the substrate structure further comprises an organic insulating layer disposed over the metal oxide semiconductor transistor and the polysilicon transistor, wherein the organic insulating layer directly contacts with the substrate in the aperture region.

9. The display device as claimed in claim 1, wherein an edge of the silicon oxide insulating layer aligns with an edge of the first gate electrode, an edge of a first source electrode or an edge of a first drain electrode, wherein the first source electrode and the first drain electrode are disposed at both sides of the first channel region.

10. The display device as claimed in claim 1, wherein a second gate electrode of the polysilicon transistor is disposed between the substrate and a polysilicon layer of the polysilicon transistor, and the first gate electrode of the metal oxide semiconductor transistor is disposed between the metal oxide semiconductor layer and the substrate.

11. A display device, comprising:

a substrate structure, comprising;

a substrate including a pixel region, and the pixel region including an aperture region;

a metal oxide semiconductor transistor disposed over the substrate and comprising;

a metal oxide semiconductor layer including a first channel region,

a first gate electrode under the first channel region; and

a gate insulating layer disposed between the first gate electrode and the metal oxide semiconductor layer, wherein the gate insulating layer includes a first silicon nitride layer and a first silicon oxide layer, and the first silicon oxide layer is disposed between the first silicon nitride layer and the metal oxide semiconductor layer;

a polysilicon transistor disposed over the substrate; and

a silicon nitride insulating layer disposed over the metal oxide semiconductor transistor and the polysilicon transistor, wherein the silicon nitride insulating layer directly contacts with the first silicon nitride layer in the aperture region;

an opposite substrate structure; and

a display medium disposed between the substrate structure and the opposite substrate structure.

12. The display device as claimed in claim 11, wherein the polysilicon transistor comprises:

a polysilicon layer including a second channel region; and

a second gate electrode on the second channel region,

wherein the polysilicon layer is disposed between the substrate and the second gate electrode, and the metal oxide semiconductor layer is disposed over the first gate electrode.

13. The display device as claimed in claim 12, wherein the polysilicon transistor further comprises an amorphous silicon layer disposed over the polysilicon layer.

14. The display device as claimed in claim 12, wherein the substrate structure further comprises a light shielding layer disposed between the polysilicon layer and the substrate, the first gate electrode is disposed between the metal oxide semiconductor layer and the substrate, and the first gate electrode and the light shielding layer are the same layer.

15. The display device as claimed in claim 11, wherein an edge of the first silicon oxide layer aligns with an edge of the first gate electrode, an edge of a first source electrode or an edge of a first drain electrode, wherein the first source electrode and the first drain electrode are disposed at both sides of the first channel region.

16. The display device as claimed in claim 11, wherein a second gate electrode of the polysilicon transistor is disposed between the substrate and a polysilicon layer of the polysilicon transistor, and the first gate electrode of the metal oxide semiconductor transistor is disposed between the metal oxide semiconductor layer and the substrate.