Array substrate and manufacturing method thereof, and display apparatus

• US 9,911,766 B2
• Filed: 06/26/2014
• Issued: 03/06/2018
• Est. Priority Date: 03/26/2014
• Status: Expired due to Fees

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Chen, Yong, Mo, Zailong, Shi, Tianlei, Park, Seungyik
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Rhodes, Juanita
• Application Number:
  US14/316,354
• Publication Number:
  US 20150279859A1
• Time in Patent Office: 1,349 Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate an array substrate, which can avoid poor displays due to large coupling capacitance between a data line and a pixel electrode in an array substrate in the prior art. The manufacturing method comprises the following steps: S1, forming a data line metal layer on a substrate, and forming a pattern of a data line by a patterning process; S2, forming a semiconductor layer on the substrate formed with the data line thereon, and forming a pattern of an active layer by a patterning process, wherein the data line is connected with the active layer.

Claims

1. A manufacturing method of an array substrate, comprising the following steps:

S1, forming a data line metal layer on a substrate, and forming a pattern of a data line by a patterning process of the data line metal layer;

S2, forming a semiconductor layer on the substrate formed with the data line thereon, and forming a pattern of an active layer by a patterning process of the semiconductor layer, wherein the data line is connected with the active layer, and wherein the step S2 further comprises;

depositing a polycrystalline silicon layer on the substrate formed with the data line thereon by a molecular beam deposition method or a low pressure chemical vapor deposition method, or first depositing an amorphous silicon layer by a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method, then forming a polycrystalline silicon layer by utilizing excimer laser annealing;

forming the pattern of the active layer by patterning the polycrystalline silicon layer;

forming an active region, a source region and a drain region by doping the active layer, wherein the source region and the drain region are located on two sides of the active region respectively, and the data line is connected with the source region; and

, after step S2,

S3, forming a gate insulator and a conducting metal layer on the substrate formed with the active layer thereon, and forming a pattern of a gate line by a patterning process of the conducting metal layer, wherein an overlapped region between projections of the gate line and the active layer on the substrate corresponds to the active region, and a part of the gate line corresponding to the overlapped region functions as a gate electrode;

wherein, in step S1, both of the pattern of the data line and a pattern of a shield metal for shielding the active region are formed by a same layer through the patterning process of the data line metal layer, and the shield metal is not electrically connected with any electrical components formed on the array substrate.

2. The manufacturing method of claim 1, wherein, before the step S2, further comprises:

forming a buffer layer on the substrate formed with the data line thereon, and forming a via hole, for connecting the data line and the source region to be formed in the active layer, in the buffer layer by a patterning process of the buffer layer.

3. The manufacturing method of claim 1, wherein, after the step S3, further comprises:

S4, forming an inter-layer dielectric and a planarization layer on the substrate formed with the gate line thereon, and forming a via hole passing through the gate insulator, the inter-layer dielectric and the planarization layer by a patterning process of the gate insulator, the inter-layer dielectric and the planarization layer, wherein the via hole will be used for connecting the drain region and a first transparent electrode to be formed;

S5, forming a first transparent conducting layer on the substrate formed with the inter-layer dielectric and the planarization layer thereon, and forming a pattern of the first transparent electrode by a patterning process of the first transparent conducting layer;

S6, forming a passivation layer and a second transparent conducting layer on the substrate formed with the first transparent electrode thereon, and forming a pattern of a second transparent electrode by a patterning process of the second transparent conducting layer.

4. The manufacturing method of claim 1, wherein, after the step S3, further comprises:

S4, forming an inter-layer dielectric, a planarization layer and a first transparent conducting layer on the substrate formed with the gate line thereon, and forming a pattern of a first transparent electrode by a patterning process of the first transparent conducting layer;

S5, forming a passivation layer on the substrate formed with the first transparent electrode thereon, and forming a via hole passing through the gate insulator, the inter-layer dielectric, the planarization layer and the passivation layer by a patterning process of the gate insulator, the inter-layer dielectric, the planarization layer and the passivation layer, wherein the via hole will be used for connecting the drain region and a second transparent electrode to be formed;

S6, forming a second transparent conducting layer on the substrate formed with the passivation layer thereon, and forming a pattern of the second transparent electrode by a patterning process of the second transparent conducting layer.

5. The manufacturing method of claim 3, wherein, the first transparent electrode is a plate-shaped electrode, and the second transparent electrode is a slit-shaped electrode.

12. The manufacturing method of claim 4, wherein, the first transparent electrode is a plate-shaped electrode, and the second transparent electrode is a slit-shaped electrode.

6. An array substrate, comprising a data line and an active layer, wherein the data line is below the active layer, and the data line is connected with the active layer,

wherein the active layer is a low temperature poly-silicon layer, and the low temperature poly-silicon layer comprises an active region, a source region and a drain region, wherein the source region and the drain region are located on two sides of the active region respectively, and the data line is connected with the source region;

and

wherein the array substrate further comprises a gate insulator and a gate line above the active layer, and an overlapped region of projections of the gate line and the active layer on a substrate corresponds to the active region, and a part of the gate line corresponding to the overlapped region functions as a gate electrode; and

wherein a pattern of a shield metal for shielding the active region of the active layer is formed by a same layer as the data line, and the shield metal is below the active layer, and the shield metal is not electrically connected with any electrical components formed on the array substrate.

7. The array substrate of claim 6, further comprising a buffer layer between the data line and the active layer, and a via hole for connecting the data line and the active layer is formed in the buffer layer.

8. The array substrate of claim 6, further comprising an inter-layer dielectric, a planarization layer, a first transparent electrode, a passivation layer and a second transparent electrode, wherein the drain region is connected with the first transparent electrode through a via hole passing through the gate insulator, the inter-layer dielectric and the planarization layer.

9. The array substrate of claim 6, further comprising an inter-layer dielectric, a planarization layer, a first transparent electrode, a passivation layer and a second transparent electrode above the gate line, and the drain region is connected with the second transparent electrode through a via hole passing through the gate insulator, the inter-layer dielectric, the planarization layer and the passivation layer.

10. The array substrate of claim 8, wherein, the first transparent electrode is a plate-shaped electrode, and the second transparent electrode is a slit-shaped electrode.

11. A display apparatus, comprising the array substrate of claim 6.

13. The array substrate of claim 9, wherein, the first transparent electrode is a plate-shaped electrode, and the second transparent electrode is a slit-shaped electrode.