Semiconductor structure with multi spacer

• US 9,911,824 B2
• Filed: 09/18/2015
• Issued: 03/06/2018
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Wang, Chih-Hao, Leung, Ying-Keung
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/858,862
• Publication Number:
  US 20170084714A1
• Time in Patent Office: 900 Days
• Field of Search: 257401, 257368, 257386, 257347, 257E21409, 257E2119, 257E21573, 438284, 438286, 438249, 438479, 438585
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.

Claims

1. A semiconductor structure, comprising:

a fin structure formed over a substrate;

a gate structure formed across the fin structure;

a bottom spacer formed on a lower part of a sidewall of the gate structure;

an upper spacer formed on an upper part of the sidewall of the gate structure, wherein the upper spacer comprises a first air gap formed in a dielectric material; and

a second air gap located adjacent to the upper spacer and separating from the bottom spacer, wherein a bottommost portion of the second air gap is at a position higher than a bottom surface of the gate structure.

2. The semiconductor structure as claimed in claim 1, further comprising:

a bottom interlayer dielectric layer formed around the bottom spacer;

an upper interlayer dielectric layer formed around the upper spacer; and

a spacer layer located between the bottom interlayer dielectric layer and the upper interlayer dielectric layer,

wherein a dielectric constant of the spacer layer is higher than a dielectric constant of the bottom interlayer dielectric layer.

3. The semiconductor structure as claimed in claim 2, wherein the second air gap is located between the spacer layer and the upper spacer.

4. The semiconductor structure as claimed in claim 2, wherein a top surface of the bottom interlayer dielectric layer is at a position that is lower than a top surface of the bottom spacer.

5. The semiconductor structure as claimed in claim 2, wherein the spacer layer and the bottom spacer are made of different materials.

6. The semiconductor structure as claimed in claim 2, wherein the spacer layer is made of aluminum oxide (Al₂O₃) or aluminum oxynitride (AlON).

15. The semiconductor structure as claimed in claim 2, wherein the dielectric constant of the spacer layer is higher than a dielectric constant of the upper interlayer dielectric layer.

19. The semiconductor structure as claimed in claim 1, wherein the second air gap is located outside a space defined by an outer surface of the bottom spacer.

20. The semiconductor structure as claimed in claim 1, wherein the second air gap is located outside a space defined by an outer surface of the upper spacer.

7. A semiconductor structure, comprising:

a fin structure formed over a substrate;

a gate structure formed across the fin structure;

a bottom spacer formed on a lower part of a sidewall of the gate structure;

a source/drain structure forming in the fin structure;

a bottom interlayer dielectric layer formed around the source/drain structure;

a spacer layer formed over the bottom interlayer dielectric layer, wherein the spacer layer and the bottom interlayer dielectric layer are made of different materials;

an upper interlayer dielectric layer formed over the spacer layer, wherein the spacer layer and the upper interlayer dielectric layer are made of different materials;

a contact formed through the upper interlayer dielectric layer over the source/drain structure; and

an upper spacer formed between the contact and an upper part of the sidewall of the gate structure,

wherein the upper spacer comprises an air gap formed in a dielectric material, and a top surface of the bottom interlayer dielectric layer is lower than a top surface of the bottom spacer.

8. The semiconductor structure as claimed in claim 7, further comprising:

a second air gap located at an end of the spacer layer.

9. The semiconductor structure as claimed in claim 7, wherein the spacer layer and the bottom spacer are made of different materials.

16. The semiconductor structure as claimed in claim 7, wherein the spacer layer is in direct contact with the upper spacer.

17. The semiconductor structure as claimed in claim 8, wherein the spacer layer and the upper spacer are separated by the second air gap.

10. A semiconductor structure, comprising:

a gate structure over a substrate;

a bottom spacer formed at a lower part of a sidewall of the gate structure;

a bottom interlayer dielectric layer formed around the bottom spacer;

a spacer layer formed over the bottom interlayer dielectric layer, wherein the spacer layer and the bottom spacer are made of different materials;

an upper spacer formed over the bottom spacer, wherein the upper spacer comprises a first air gap formed in a dielectric material, and the upper spacer is thicker than the bottom spacer; and

a second air gap formed over the spacer layer and exposing a portion of the upper spacer.

11. The semiconductor structure as claimed in claim 10, further comprising:

an upper interlayer dielectric layer formed over the spacer layer, wherein the spacer layer and the upper interlayer dielectric layer are made of different materials.

12. The semiconductor structure as claimed in claim 11,

wherein the second air gap separates the spacer layer and the upper spacer.

13. The semiconductor structure as claimed in claim 10, wherein the spacer layer is made of aluminum oxide (Al₂O₃) or aluminum oxynitride (AlON).

14. The semiconductor structure as claimed in claim 10, wherein the bottom spacer has a height in a range from about 20 nm to about 60 nm.

18. The semiconductor structure as claimed in claim 10, wherein the spacer layer extends in a direction substantially parallel with a top surface of the substrate.